5-stage pipelined 32-bit MIPS microprocessor in Verilog

It's all coming back into focus!

A computer system containing CPU, OS and Compiler under MIPS architecture.

5 stage pipelined MIPS-32 processor

Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)

✔️ Examples to learn Mips

A classic 5-stage pipeline MIPS 32-bit processor. solve every hazard with stall

Linux kernel source tree with the latest features and modifications to unleash the full potential of Ingenic processors.

Some of my assembly code (examples, iterative and recursive algorithms) from Computer's Architecture course in Sapienza University, CS Bachelor's Degree 💾

A snake game developed in assembly for MIPS processor

A C/C++ header file that converts Intel SSE intrinsics to MIPS/MIPS64 MSA intrinsics.

Pipelined MIPS architecture created in Verilog. Includes data forwarding and hazard detection.

MIPS architecture implemented in Verilog.

A Simple 5-stage 32-bit pipelined processor with Harvard architecture and a RISC-like instruction set architecture.

Bubble Sort in MIPS

32-bit MIPS CPU

MIPS programs with MARS system calls

This is a MIPS 5 stage 32-bit pipelined processor with Harvard architecture, which comes with an assembler to interpret instructions to supported OP codes.

Assignment from the Advanced Computer Architecture class.