MIPS 5 Stage Pipelined Processor

This is a MIPS 5 stage 32-bit pipelined processor with Harvard architecture, which comes with an assembler to interpret instructions to supported OP codes.

Design

you can check the design here Design

Features

• Supports 8 registers from R1 to R7
• Supports Reset signal
• Reading and writing to ports
• Data hazard detection & handling using:
  • ALU-forwarding
  • Memory-forwarding
  • Stalling for load-use case
• Control hazard detection & handling

Stages

• Fetch
• Decode
• Execute
• Memory
• Write Back

IR format

Instruction Type	Immediate or register	Code	Rdest	Rsrc	Offset / Immediate value
31-30 (2 bits)	29 (1 bit)	28-24 (5 bits)	23-20 (4 bits)	19-16 (4 bits)	15-0 (16 bits)

General components of an instruction opcode

0-operand or 1-operand	2-operands	Memory	Change of control
00	01	10	11

Supported instructions

NO OP	One OP	Two OP	Memory
NOP	CLR	MOV	PUSH
SETC	NOT	ADD	POP
CLRC	INC	SUB	LDD
	NEG	AND	STD
	DEC	OR
	OUT	IADD
	IN	SHL
	RLC	SHR
	RRC	LDM

Run

• Write your program then run the assembler to convert it to binary file

  python main.py <input_file_path> <output_file_path>
  

• Create your project in modelsim with a work library name.

• Add all the .vhd files in src to the project.

• Compile all files.

• Then start simulation with cpu-arch

• Make sure to change the directory of memory files in the do files before use them.

Contributors

Bahaa Eldeen

Eman Othman

Tarek Samy

Ebrahim Gomaa

License

This software is licensed under MIT License, See MIT licensed