Add support of power management for stm32 SAES peripheral

core/arch/arm/dts/stm32mp13xc.dtsi

@@ -18,7 +18,8 @@
 		compatible = "st,stm32mp13-saes";
 		reg = <0x54005000 0x400>;
 		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&rcc SAES_K>;
+		clocks = <&rcc SAES_K>, <&rcc RNG1_K>;
+		clock-names = "bus", "rng";
 		resets = <&rcc SAES_R>;
 		status = "disabled";
 	};

core/arch/arm/dts/stm32mp13xf.dtsi

@@ -18,7 +18,8 @@
 		compatible = "st,stm32mp13-saes";
 		reg = <0x54005000 0x400>;
 		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&rcc SAES_K>;
+		clocks = <&rcc SAES_K>, <&rcc RNG1_K>;
+		clock-names = "bus", "rng";
 		resets = <&rcc SAES_R>;
 		status = "disabled";
 	};

core/arch/arm/plat-stm32mp1/conf.mk

@@ -249,6 +249,14 @@ $(call force,CFG_STM32_I2C,y)
 $(call force,CFG_STM32_GPIO,y)
 endif
 
+# SAES and CRYP cannot be registered at the same time in the crypto framework.
+# If CRYP and SAES are enable on STMP32MP13, disable CRYP for safety purpose
+ifeq ($(CFG_STM32MP13),y)
+ifeq ($(call cfg-all-enabled, CFG_STM32_CRYP CFG_STM32_SAES), y)
+override CFG_STM32_CRYP := n
+endif # cfg-all-enabled, CFG_STM32_CRYP CFG_STM32_SAES
+endif # CFG_STM32MP13
+
 # If any crypto driver is enabled, enable the crypto-framework layer
 ifeq ($(call cfg-one-enabled, CFG_STM32_CRYP CFG_STM32_SAES),y)
 $(call force,CFG_STM32_CRYPTO_DRIVER,y)

core/drivers/crypto/stm32/stm32_saes.c

@@ -13,6 +13,7 @@
 #include <kernel/dt.h>
 #include <kernel/huk_subkey.h>
 #include <kernel/mutex.h>
+#include <kernel/pm.h>
 #include <libfdt.h>
 #include <mm/core_memprot.h>
 #include <stdint.h>
@@ -142,6 +143,7 @@ static struct mutex saes_lock = MUTEX_INITIALIZER;
 static struct stm32_saes_platdata {
 	vaddr_t base;
 	struct clk *clk;
+	struct clk *clk_rng;
 	struct rstctrl *reset;
 } saes_pdata;
 
@@ -1363,10 +1365,6 @@ static TEE_Result stm32_saes_parse_fdt(struct stm32_saes_platdata *pdata,
 	    dt_saes.reg_size == DT_INFO_INVALID_REG_SIZE)
 		return TEE_ERROR_BAD_PARAMETERS;
 
-	res = clk_dt_get_by_index(fdt, node, 0, &pdata->clk);
-	if (res != TEE_SUCCESS)
-		return res;
-
 	res = rstctrl_dt_get_by_index(fdt, node, 0, &pdata->reset);
 	if (res != TEE_SUCCESS && res != TEE_ERROR_ITEM_NOT_FOUND)
 		return res;
@@ -1376,23 +1374,15 @@ static TEE_Result stm32_saes_parse_fdt(struct stm32_saes_platdata *pdata,
 	if (!pdata->base)
 		panic();
 
-	return TEE_SUCCESS;
-}
-
-static TEE_Result stm32_saes_probe(const void *fdt, int node,
-				   const void *compat_data __unused)
-{
-	TEE_Result res = TEE_SUCCESS;
-
-	assert(!saes_pdata.base);
-
-	res = stm32_saes_parse_fdt(&saes_pdata, fdt, node);
+	res = clk_dt_get_by_name(fdt, node, "bus", &pdata->clk);
 	if (res)
 		return res;
 
-	if (clk_enable(saes_pdata.clk))
-		panic();
+	return clk_dt_get_by_name(fdt, node, "rng", &pdata->clk_rng);
+}
 
+static void stm32_saes_reset(void)
+{
 	if (saes_pdata.reset) {
 		/* External reset of SAES */
 		if (rstctrl_assert_to(saes_pdata.reset, TIMEOUT_US_1MS))
@@ -1408,6 +1398,46 @@ static TEE_Result stm32_saes_probe(const void *fdt, int node,
 		udelay(SAES_RESET_DELAY);
 		io_clrbits32(saes_pdata.base + _SAES_CR, _SAES_CR_IPRST);
 	}
+}
+
+static TEE_Result stm32_saes_pm(enum pm_op op, uint32_t pm_hint,
+				const struct pm_callback_handle *hdl __unused)
+{
+	switch (op) {
+	case PM_OP_SUSPEND:
+		clk_disable(saes_pdata.clk);
+		clk_disable(saes_pdata.clk_rng);
+		return TEE_SUCCESS;
+
+	case PM_OP_RESUME:
+		if (clk_enable(saes_pdata.clk) ||
+		    clk_enable(saes_pdata.clk_rng))
+			panic();
+
+		if (PM_HINT_IS_STATE(pm_hint, CONTEXT))
+			stm32_saes_reset();
+
+		return TEE_SUCCESS;
+	default:
+		break;
+	}
+
+	return TEE_ERROR_NOT_IMPLEMENTED;
+}
+
+static TEE_Result stm32_saes_probe(const void *fdt, int node,
+				   const void *compat_data __unused)
+{
+	TEE_Result res = TEE_ERROR_GENERIC;
+
+	res = stm32_saes_parse_fdt(&saes_pdata, fdt, node);
+	if (res)
+		return res;
+
+	if (clk_enable(saes_pdata.clk) || clk_enable(saes_pdata.clk_rng))
+		panic();
+
+	stm32_saes_reset();
 
 	if (IS_ENABLED(CFG_CRYPTO_DRV_CIPHER)) {
 		res = stm32_register_cipher(SAES_IP);
@@ -1417,6 +1447,8 @@ static TEE_Result stm32_saes_probe(const void *fdt, int node,
 		}
 	}
 
+	register_pm_core_service_cb(stm32_saes_pm, NULL, "stm32-saes");
+
 	return TEE_SUCCESS;
 }