plat-versal: add support for the Versal Net variant #6738

jcorbier · 2024-03-05T17:30:10Z

This series upgrades the AMD/Xilinx port with the following:

Add support for a new SoC in the Versal family
Add a hardware crypto accelerator driver for this specific SoC
Fixes for more recent versions of the Xilinx software environment (PLM APIs have changed in 2023)

Versal Net is a new SoC flavor based on the Versal architecture. This commit introduces it in versal platform code. Signed-off-by: Jeremie Corbier <jeremie.corbier@provenrun.com>

Make it more generic and still provide a default IPI channel to the PMC for the other drivers. Signed-off-by: Jeremie Corbier <jeremie.corbier@provenrun.com>

PLM HWRNG driver cannot provide more than 32 bytes of entropy at a time. Split bigger requests into 32 bytes chunks. Signed-off-by: Jeremie Corbier <jeremie.corbier@provenrun.com>

The Versal Net variant comes with a dedicated PKI engine. This driver makes use of the engine for ECDSA P-256, P-384, and P-521 sign, verify and key generation operations. Signed-off-by: Jeremie Corbier <jeremie.corbier@provenrun.com>

The original HUK driver generated the HUK using SHA-256. This commit replaces this mechanism with the more robust HKDF-SHA256. Signed-off-by: Jeremie Corbier <jeremie.corbier@provenrun.com>

Add simple PTA allowing to dynamically load data in the Versal PL. Signed-off-by: Jeremie Corbier <jeremie.corbier@provenrun.com>

- update crypto API IDs - update calls to the KAT subsystem Signed-off-by: Jeremie Corbier <jeremie.corbier@provenrun.com>

The XilNvm API has heavily changed between Versal and Versal Net. This commit adds support for the Net variant. Signed-off-by: Jeremie Corbier <jeremie.corbier@provenrun.com>

XilSecure has been updated to pack the public exponent right after the modulus rather than at a fixed 512 bytes (RSA 4096 key size) offset. See commit below for more details: Xilinx/embeddedsw@c2dd2eb Signed-off-by: Jeremie Corbier <jeremie.corbier@provenrun.com>

ldts · 2024-03-06T10:25:47Z

thanks @jcorbier

I need to ask that the changes to support the more recent AMD/Xilinx tools maintain backwards compatibility. We should be able to query the ABI at runtime - maybe even propose whatever is needed to AMD/Xilinx https://github.com/Xilinx/embeddedsw .

I'd like to understand as well the level of testing that has been done with this software (just the output of xtest, to check if you encountered any regressions (ie this is the changelog for 4.1.0 #6574 (comment) ).

Thirdly is there anything that you also plan on posting to https://github.com/OP-TEE/optee_docs ?

jcorbier · 2024-03-06T10:38:16Z

Thanks @ldts for your feedback.

I need to ask that the changes to support the more recent AMD/Xilinx tools maintain backwards compatibility. We should be able to query the ABI at runtime - maybe even propose whatever is needed to AMD/Xilinx https://github.com/Xilinx/embeddedsw .

Noted. Let me see how best we can implement that.

I'd like to understand as well the level of testing that has been done with this software (just the output of xtest, to check if you encountered any regressions (ie this is the changelog for 4.1.0 #6574 (comment) ).

I don't have access to the logs right now but the current state is the same as for Versal in 4.1.0.

Thirdly is there anything that you also plan on posting to https://github.com/OP-TEE/optee_docs ?

Yes, a working version is available here https://github.com/ProvenRun/optee_docs/tree/versal_net_port
It needs some additional work before I create a pull request for it though.

Same thing for build and manifest repositories.

ldts · 2024-03-08T11:06:39Z

we should split the drivers (rng/nvm) into a different files (versal_net_rng, versal_net_nvm?)

jcorbier · 2024-03-08T13:39:45Z

we should split the drivers (rng/nvm) into a different files (versal_net_rng, versal_net_nvm?)

Agreed, the initial thinking for the current implementation was to avoid as much code duplication as possible between versal and versal_net but in the end it makes things much more complicated than needed.

nathan-menhorn · 2024-03-12T15:08:46Z

Hi @jcorbier any updates on this PR?

jcorbier · 2024-03-12T15:47:37Z

Hi @jcorbier any updates on this PR?

Hi @nathan-menhorn, still working out the details of what needs to be done to properly split versal/versal-net code, including the TRNG update. I'll try and push an update to this PR by end of this week.

etienne-lms · 2024-03-14T10:54:28Z

core/arch/arm/plat-versal/conf.mk

+CFG_RPMB_FS ?= n
+CFG_RPMB_TESTKEY ?= y
+CFG_RPMB_WRITE_KEY ?=y


Intentionally appling these default configs to all Versal flavors?
Same question for CFG_VERSAL_MBOX_IPI_ID ?= 1 and CFG_VERSAL_FPGA_LOADER_PTA ?= y.

Should be addressed by fixup commit 9dd3ef9

etienne-lms · 2024-03-14T10:57:09Z

core/arch/arm/plat-versal/conf.mk

+CFG_VERSAL_PKI_COUNTER_MEASURES ?= n
+CFG_VERSAL_PKI_PWCT ?= y
+endif
+endif


prefer with a comment : endif # PLATFORM_FLAVOR is net

Should be addressed by fixup commit 9dd3ef9

etienne-lms · 2024-03-14T10:58:36Z

core/arch/arm/plat-versal/conf.mk

@@ -23,17 +27,31 @@ CFG_CORE_DYN_SHM   ?= y
 CFG_WITH_STATS     ?= y
 CFG_ARM64_core     ?= y

+# Default Versal NET memory allocation


Would be better to have the inline comment inside the config block:

ifeq ($(PLATFORM_FLAVOR),net) +# Default Versal NET memory allocation ... else +# Default Versal memory allocation ... endif

or alternatively:

+# Default memory allocation ifeq ($(PLATFORM_FLAVOR),net) ... else ... endif

Should be addressed by fixup commit 9dd3ef9

etienne-lms · 2024-03-14T11:05:04Z

core/pta/versal/fpga_pta.c

+
+pseudo_ta_register(.uuid = PTA_VERSAL_FPGA_UUID, .name = FPGA_PTA_NAME,
+		   .flags = PTA_DEFAULT_FLAGS,
+		   .invoke_command_entry_point = invokeCommandEntryPoint);


prefer snake case, e.g. s/invokeCommandEntryPoint/invoke_command/g

Should be addressed by commit 1dd1efa

etienne-lms · 2024-03-14T11:07:14Z

core/pta/versal/fpga_pta.c

+	case PTA_VERSAL_FPGA_WRITE:
+		return pta_versal_fpga_write(param_types, params);
+	default:
+		return TEE_ERROR_BAD_PARAMETERS;


Prefer TEE_ERROR_NOT_SUPPORTED or TEE_ERROR_NOT_IMPLEMENTED.
TEE_ERROR_BAD_PARAMETERS refers the invocation parameters.

Should be addressed by fixup commit 1dd1efa

etienne-lms · 2024-03-20T10:10:07Z

core/drivers/versal_mbox.c

+	[33] = "EFUSE_READ_CACHE",
+	[34] = "EFUSE_RELOAD_N_PRGM_PROT_BITS",
+	[35] = "EFUSE_INVALID",
+


can remove this empty line

etienne-lms · 2024-03-20T10:10:58Z

core/drivers/crypto/versal/ecc.c

+				       sdata->message.data,
+				       sdata->message.length,
+				       sdata->signature.data,
+				       sdata->signature.length);


add braces : if (ret == TEE_ERROR_NOT_SUPPORTED) { ... }

Ditto at line 133

etienne-lms · 2024-03-20T10:11:56Z

core/drivers/crypto/versal/ecc_mbox.c

+#include <tee/tee_cryp_utl.h>
+#include <util.h>
+#include <io.h>
+#include <config.h>


sort by header file name alphabetical order.

etienne-lms · 2024-03-20T10:13:25Z

core/drivers/versal_mbox.c

+	if (!mem)
+		return TEE_ERROR_BAD_PARAMETERS;
+
+	free(mem->buf);


I strongly suggest to also set mem->buf = NULL

Should be addressed by fixup commit 6d01a34

etienne-lms · 2024-03-20T10:14:05Z

core/drivers/versal_mbox.c

+	/* Wait for remote to acknowledge the interrupt */
+	do {
+		status = io_read32(ipi->regs + IPI_OBR_OFFSET);
+	} while (status & IPI_BIT_MASK(ipi->rmt));


timeout? (maybe see IO_READ32_POLL_TIMEOUT())

@jcorbier a timeout would be good here. If the remote processor hangs and never responds then this will hang the mailbox driver/OP-TEE.

Should be addressed by fixup commit 6d01a34

ldts · 2024-03-31T19:17:50Z

@etienne-lms could you hold your comments until the patchset is updated please?

There are a couple of functional changes that need addressing first

ABI runtime detection (not only to support the older toolchain but also to be covered for changes in the future)
use different files for Versal net instead of conditional macros (since some drivers are radically different).

So I suggest we wait for that before we go into details (ie default configs, coding standards and so on) as some files will change quite a bit

Split NVM code into two seperate drivers, one for Versal, one for Versal Net, since both variants have very different NVM PLM code. Signed-off-by: Jeremie Corbier <jeremie.corbier@provenrun.com>

jcorbier · 2024-04-02T14:12:21Z

@etienne-lms could you hold your comments until the patchset is updated please?

Indeed, I'll be pusing fixup commits in the coming hours/days.

- Do not enable RPMB configs on Versal - Do not modify Versal IPI ID - Do not enable FPGA PTA on Versal Signed-off-by: Jeremie Corbier <jeremie.corbier@provenrun.com>

- s!invokeCommandEntryPoint!invoke_command! - Return TEE_ERROR_NOT_SUPPORTED rather than BAD_PARAMS in case an invalid command ID is used - Re-order includes as requested Signed-off-by: Jeremie Corbier <jeremie.corbier@provenrun.com>

- Add timeout in case the remote processor is unresponsive - versal_mbox_free explicitely sets the pointer to NULL Signed-off-by: Jeremie Corbier <jeremie.corbier@provenrun.com>

etienne-lms · 2024-04-02T17:39:27Z

core/drivers/crypto/versal/ecc.c

-#define XSECURE_ECDSA_KAT_NIST_P384	0
-#define XSECURE_ECDSA_KAT_NIST_P521	2
+#include <io.h>
+#include <config.h>


sort alphabetically

etienne-lms · 2024-04-02T17:40:58Z

core/drivers/crypto/versal/ecc.c


+	memcpy_swp(pad, from, sz);


assert(sz <= sizeof(pad))

etienne-lms · 2024-04-02T17:41:53Z

core/drivers/crypto/versal/ecc.c

-		    sdata->message.length,
-		    sdata->signature.data,
-		    &sdata->signature.length);
+	TEE_Result ret;


Initialization value missing, here and at line 146.

etienne-lms · 2024-04-02T17:46:14Z

core/drivers/crypto/versal/ecc_mbox.c

+					      TEE_TYPE_ECDSA_KEYPAIR, bits);
+	if (ret) {
+		EMSG("Versal, can't allocate the ephemeral key");
+		versal_mbox_free(&p);


suggestion: goto out1.
ditto at lines 218/219.

etienne-lms · 2024-04-02T19:29:30Z

core/pta/versal/fpga_pta.c

+					TEE_Param params[TEE_NUM_PARAMS])
+{
+	uint8_t *buf;
+	size_t bufsize;


init values

Hi @etienne-lms same comment as the versal_net_nvm.c comment.

etienne-lms · 2024-04-03T07:58:01Z

core/drivers/versal_net_nvm.c

+{
+	struct versal_efuse_misc_ctrl_bits misc_ctrl;
+
+	memset(&misc_ctrl, 0, sizeof(struct versal_efuse_misc_ctrl_bits));


- struct versal_efuse_misc_ctrl_bits misc_ctrl; - - memset(&misc_ctrl, 0, sizeof(struct versal_efuse_misc_ctrl_bits)); + struct versal_efuse_misc_ctrl_bits misc_ctrl = { };

etienne-lms · 2024-04-03T07:59:13Z

core/drivers/versal_net_nvm.c

+TEE_Result versal_efuse_read_user_data(uint32_t *buf, size_t len,
+				       uint32_t first, size_t num)
+{
+	uint16_t offset;


Initialization value missing.
Many other occurrences in this source file.

Initialization value missing. Many other occurrences in this source file.

Hi @etienne-lms as these variables are not volatile is initialization necessary as the compiler will optimize the init out since offset is populated just below at L397. Should these be volatile as well to ensure initialization?

Initializing local variables where defined is part of the OP-TEE OS coding standard.

etienne-lms · 2024-04-03T07:59:46Z

core/drivers/versal_net_nvm.c

+	buf->puf_hd_invalid = ((puf_ctrl & BIT(30)) >> 30);
+	buf->puf_test2_dis = ((puf_ctrl & BIT(29)) >> 29);
+	buf->puf_dis = ((sec_ctrl & BIT(18)) >> 18);
+	buf->puf_syn_lk = ((sec_ctrl & BIT(16)) >> 16);


remove outer parentheses.

etienne-lms · 2024-04-03T08:01:03Z

core/drivers/versal_pm.c

-#define VERSAL_PM_MAJOR		0
-#define VERSAL_PM_MINOR		1
+#define VERSAL_PM_MAJOR		1
+#define VERSAL_PM_MINOR		0


Deserves a specific commit IMHO.

etienne-lms · 2024-04-03T08:04:45Z

core/drivers/crypto/versal/authenc.c

-	free(key.buf);
-	free(init_buf.buf);
-	free(nonce.buf);
+	versal_mbox_free(&nonce);


since versal_mbox_free() NULL's the internal buffer reference, you don't need these numerous branch labels. The below instructions are enough:

error: versal_mbox_free(&nonce); versal_mbox_free(&init_buf); versal_mbox_free(&key); return ret;

nathan-menhorn · 2024-05-07T21:54:57Z

Hi @jcorbier what's the current status of this PR? Thanks.

jcorbier added 9 commits March 5, 2024 18:04

plat-versal: add support for Versal Net variant

9f1cd1b

Versal Net is a new SoC flavor based on the Versal architecture. This commit introduces it in versal platform code. Signed-off-by: Jeremie Corbier <jeremie.corbier@provenrun.com>

drivers: versal: rework mbox driver

0b8feb3

Make it more generic and still provide a default IPI channel to the PMC for the other drivers. Signed-off-by: Jeremie Corbier <jeremie.corbier@provenrun.com>

drivers: versal: use PLM for generic RNG operations

e0f5515

PLM HWRNG driver cannot provide more than 32 bytes of entropy at a time. Split bigger requests into 32 bytes chunks. Signed-off-by: Jeremie Corbier <jeremie.corbier@provenrun.com>

drivers: versal: PKI engine driver for Versal Net

5f23b2b

The Versal Net variant comes with a dedicated PKI engine. This driver makes use of the engine for ECDSA P-256, P-384, and P-521 sign, verify and key generation operations. Signed-off-by: Jeremie Corbier <jeremie.corbier@provenrun.com>

drivers: versal: use HKDF to derive the HUK

5e0d4a9

The original HUK driver generated the HUK using SHA-256. This commit replaces this mechanism with the more robust HKDF-SHA256. Signed-off-by: Jeremie Corbier <jeremie.corbier@provenrun.com>

core: pta: add Versal FPGA PTA

caf9ea9

Add simple PTA allowing to dynamically load data in the Versal PL. Signed-off-by: Jeremie Corbier <jeremie.corbier@provenrun.com>

drivers: versal: update to support more recent versions of the PLM

9267cb6

- update crypto API IDs - update calls to the KAT subsystem Signed-off-by: Jeremie Corbier <jeremie.corbier@provenrun.com>

drivers: versal: NVM driver for Versal Net

10d334a

The XilNvm API has heavily changed between Versal and Versal Net. This commit adds support for the Net variant. Signed-off-by: Jeremie Corbier <jeremie.corbier@provenrun.com>

etienne-lms reviewed Mar 20, 2024

View reviewed changes

fixup! drivers: versal: NVM driver for Versal Net

d477ff3

Split NVM code into two seperate drivers, one for Versal, one for Versal Net, since both variants have very different NVM PLM code. Signed-off-by: Jeremie Corbier <jeremie.corbier@provenrun.com>

jcorbier added 3 commits April 2, 2024 17:06

fixup! plat-versal: add support for Versal Net variant

9dd3ef9

- Do not enable RPMB configs on Versal - Do not modify Versal IPI ID - Do not enable FPGA PTA on Versal Signed-off-by: Jeremie Corbier <jeremie.corbier@provenrun.com>

fixup! core: pta: add Versal FPGA PTA

1dd1efa

- s!invokeCommandEntryPoint!invoke_command! - Return TEE_ERROR_NOT_SUPPORTED rather than BAD_PARAMS in case an invalid command ID is used - Re-order includes as requested Signed-off-by: Jeremie Corbier <jeremie.corbier@provenrun.com>

fixup! drivers: versal: rework mbox driver

6d01a34

- Add timeout in case the remote processor is unresponsive - versal_mbox_free explicitely sets the pointer to NULL Signed-off-by: Jeremie Corbier <jeremie.corbier@provenrun.com>

etienne-lms reviewed Apr 3, 2024

View reviewed changes

plat-versal: add support for the Versal Net variant #6738

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plat-versal: add support for the Versal Net variant #6738

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jcorbier commented Mar 5, 2024

ldts commented Mar 6, 2024 • edited

jcorbier commented Mar 6, 2024

ldts commented Mar 8, 2024

jcorbier commented Mar 8, 2024

nathan-menhorn commented Mar 12, 2024

jcorbier commented Mar 12, 2024

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ldts commented Mar 31, 2024

jcorbier commented Apr 2, 2024

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etienne-lms Apr 3, 2024 • edited

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nathan-menhorn commented May 7, 2024

ldts commented Mar 6, 2024 •

edited

etienne-lms Apr 3, 2024 •

edited