verilog
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Veryl: A Modern Hardware Description Language
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Jun 10, 2024 - Rust
BDD Gherkin implementation in native SystemVerilog, based on UVM.
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Jun 10, 2024 - SystemVerilog
XLS: Accelerated HW Synthesis
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Jun 10, 2024 - C++
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
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Jun 10, 2024 - Verilog
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
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Jun 10, 2024 - Verilog
Processador RISC-V multi ciclo com implementação RV32I construído em alguns dias de folga.
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Jun 10, 2024 - Verilog
Sol-1: A CPU/Computer System made from 74 series logic.
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Jun 10, 2024 - C
A (mostly) EDTASM+ compatible MC6809 Assembler using yacc/bison
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Jun 10, 2024 - C
Verilator open-source SystemVerilog simulator and lint system
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Jun 10, 2024 - C++
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
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Jun 10, 2024 - Jupyter Notebook
Opensource DDR3 Controller
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Jun 10, 2024 - Verilog
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