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Pull requests: chipsalliance/chisel
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Implement typeName API for stable Module names (backport #3130)
conflicts
Feature
New feature, will be included in release notes
Please Merge
Accepted PRs that are ready to be merged. Useful when waiting on CI.
#4145
opened Jun 5, 2024 by
mergify
bot
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8 of 16 tasks
Update sbt to 1.9.9
Internal
Internal change, does not affect users, will be included in release notes
#4139
opened Jun 2, 2024 by
scala-steward
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Update sbt-assembly to 2.1.5
Internal
Internal change, does not affect users, will be included in release notes
#4130
opened Jun 2, 2024 by
scala-steward
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Support views of ports in ChiselSim (backport #4107)
Backport
Automated backport, please consider for minor release
Bugfix
Fixes a bug, will be included in release notes
#4109
opened May 29, 2024 by
mergify
bot
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5 of 14 tasks
Add Attribute annotation back to chisel in-tree firrtl
API Modification
#4023
opened Apr 22, 2024 by
lordspacehog
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7 of 14 tasks
use versionfile for mill
Internal
Internal change, does not affect users, will be included in release notes
No Release Notes
Exclude from release notes, consider using Internal instead
toBigInt should round identically for Double and BigDecimal (backport #3921)
Backport
Automated backport, please consider for minor release
bp-conflict
Bugfix
Fixes a bug, will be included in release notes
#3925
opened Mar 12, 2024 by
mergify
bot
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5 of 14 tasks
Fix ChiselStage and Builder handling of logging (backport #3895)
Backport
Automated backport, please consider for minor release
bp-conflict
Bugfix
Fixes a bug, will be included in release notes
#3896
opened Mar 1, 2024 by
mergify
bot
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6 of 14 tasks
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