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1. Innovus_NanoRoute_RT01_routed_testcases_Blocking-CLK_path Innovus_NanoRoute_RT01_routed_testcases_Blocking-CLK_path Public

   Detailed routed RT01 and other testcases with Innovus NanoRoute; includes RT01 random blockages. Example routes include CLK paths avoiding all blockages and connecting all DFF pins. All modules are…

   1

2. Spiking_Neural_Synapse_CMOS180 Spiking_Neural_Synapse_CMOS180 Public

   Analog circuits for a Spiking Neuron (and Synapse) in CMOS 180 nm, Cadence ADE XL (Monte Carlo) and ADE_L (Nominal) simulations.

   2

3. rng_self_calib rng_self_calib Public

   Digital CPU peripheral module for calibration of a pseudo-random-number generator. In CMOS gsclk45 nm, verilog RTL-Compiler (RC) synthesis and Innovus placement and layout.

   Verilog

4. Analog-CMOS-Systems-and-circuits-for-2D-3D-Localization Analog-CMOS-Systems-and-circuits-for-2D-3D-Localization Public

   This is a novel application of active analog circuits for computing the Cartesian coordinates of points ( targets ) in 2D and 3D space. Two anchors ( points ) are assumed available, with known coor…

   SourcePawn 1

5. ALU_4_bit_4_ops_mitll_fdsoi_process ALU_4_bit_4_ops_mitll_fdsoi_process Public

   ALU with 4 operations 1) 4 bit carry look ahead adder 2) 4 bit 1’s complimentary 3) 4 bit 2’s complimentary 4) 4bitAddtraction in 4 bits, done in process mitll_fdsoi, schametics to layout