Layout-Design-of-an-8x8-SRAM-array

The project is about building an 8-row by 8-bit SRAM memory array, using 65nm CMOS technology. Using a 3-to-8 decoder, the SRAM array is accessed by a 3-bit address. The SRAM cells are designed to achieve lowest power consumption and suitable static noise margin, while operating at 100 MHz Read & Write cycles. The test-bench, the implementation, and the layout of the SRAM array and the decoder are done using Cadence Virtuoso’s Analog-Design Environment (ADE). Static Noise Margin plots & calculation are obtained through Matlab scripts.

System Block Diagram

6T SRAM Cell Design

1) Static Noise Margin

Use the Read & the Write testbenches on Virtuoso to sweep Vout against Vin, & save the waveforms as csv files. Then, SNM is found by running the Matlab script "snm.m" for Read SNM & "snm_write.m" for Write SNM. The idea is to draw 45 degree lines that intersect with the 2 characteristic curves of the SRAM cell obtained from Virtuoso's csv files. The intersections are found using "InterX.m" script (https://github.com/mattools/matGeom/blob/master/matGeom/polygons2d/private/InterX.m)
& the longest diagonal between the characteristic curves is used to draw the SNM squares.

Check this document for more on how to find the SNM of the SRAM cell:
https://www.researchgate.net/file.PostFileLoader.html?id=54be4ae2d2fd64fb0d8b45cf&assetKey=AS%3A273675910090788%401442260829994

(You can just download my Matlab folders that include the csv files & Matlab scripts, & run "snm.m" & "snm_write.m" on Matlab to see the output as an example)

2) Transient Simulations

3-to-8 Decoder

Whole System's Layout

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References

• EE224 Material:
  https://drive.google.com/drive/folders/1Zzhp3N0b08uaHG6FsoPNOPavNcZDvxHt?usp=sharing
  
• Project's drive:
  https://drive.google.com/drive/folders/1NHy1KgwGcolrpJ8-mpBILm4kuQtalKxd?usp=sharing
  
• Video on how to do layout on Cadence Virtuoso:
  https://www.youtube.com/watch?v=W5aglIZuel4