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[SDAG][X86] Extend SplitVecOp_VSETCC for STRICT_FSETCC. #92509
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@llvm/pr-subscribers-backend-x86 @llvm/pr-subscribers-llvm-selectiondag Author: Freddy Ye (FreddyLeaf) ChangesFull diff: https://github.com/llvm/llvm-project/pull/92509.diff 2 Files Affected:
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index cd858003cf03b..6ddb6dc4dd871 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -3033,6 +3033,7 @@ bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
"operand!\n");
case ISD::VP_SETCC:
+ case ISD::STRICT_FSETCC:
case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;
case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break;
case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
@@ -3997,14 +3998,16 @@ SDValue DAGTypeLegalizer::SplitVecOp_TruncateHelper(SDNode *N) {
}
SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
+ bool isStrict = N->getOperand(N->getOpcode() == ISD::STRICT_FSETCC;
assert(N->getValueType(0).isVector() &&
- N->getOperand(0).getValueType().isVector() &&
+ N->getOperand(isStrict ? 1 : 0).getValueType().isVector() &&
"Operand types must be vectors");
// The result has a legal vector type, but the input needs splitting.
SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes;
SDLoc DL(N);
- GetSplitVector(N->getOperand(0), Lo0, Hi0);
- GetSplitVector(N->getOperand(1), Lo1, Hi1);
+ GetSplitVector(N->getOperand(isStrict ? 1 : 0), Lo0, Hi0);
+ GetSplitVector(N->getOperand(isStrict ? 2 : 1), Lo1, Hi1);
+
auto PartEltCnt = Lo0.getValueType().getVectorElementCount();
LLVMContext &Context = *DAG.getContext();
@@ -4014,6 +4017,16 @@ SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
if (N->getOpcode() == ISD::SETCC) {
LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
+ } else if (N->getOpcode() == ISD::STRICT_FSETCC) {
+ LoRes = DAG.getNode(ISD::STRICT_FSETCC, DL,
+ DAG.getVTList(PartResVT, N->getValueType(1)),
+ N->getOperand(0), Lo0, Lo1, N->getOperand(3));
+ HiRes = DAG.getNode(ISD::STRICT_FSETCC, DL,
+ DAG.getVTList(PartResVT, N->getValueType(1)),
+ N->getOperand(0), Hi0, Hi1, N->getOperand(3));
+ SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
+ LoRes.getValue(1), HiRes.getValue(1));
+ ReplaceValueWith(SDValue(N, 1), NewChain);
} else {
assert(N->getOpcode() == ISD::VP_SETCC && "Expected VP_SETCC opcode");
SDValue MaskLo, MaskHi, EVLLo, EVLHi;
diff --git a/llvm/test/CodeGen/X86/vec-strict-cmp-512-skx.ll b/llvm/test/CodeGen/X86/vec-strict-cmp-512-skx.ll
new file mode 100644
index 0000000000000..ccb0cd564ed1f
--- /dev/null
+++ b/llvm/test/CodeGen/X86/vec-strict-cmp-512-skx.ll
@@ -0,0 +1,22 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64 -mcpu=skx | FileCheck %s --check-prefixes=SKX
+
+; Test not crash for 512 targets but not prefer 512 vector width
+define <16 x i32> @test_v16f32_oeq_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; SKX-LABEL: test_v16f32_oeq_q:
+; SKX: # %bb.0:
+; SKX-NEXT: vcmpeqps %ymm7, %ymm5, %k1
+; SKX-NEXT: vcmpeqps %ymm6, %ymm4, %k2
+; SKX-NEXT: vpblendmd %ymm0, %ymm2, %ymm0 {%k2}
+; SKX-NEXT: vpblendmd %ymm1, %ymm3, %ymm1 {%k1}
+; SKX-NEXT: retq
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"oeq",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+declare <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(<16 x float>, <16 x float>, metadata, metadata)
+
+attributes #0 = { nounwind strictfp "min-legal-vector-width"="0" }
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py | ||
; RUN: llc < %s -mtriple=x86_64 -mcpu=skx | FileCheck %s --check-prefixes=SKX | ||
|
||
; Test not crash for 512 targets but not prefer 512 vector width |
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Comment grammar
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%res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b | ||
ret <16 x i32> %res | ||
} | ||
|
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Test more vector types
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This patch is to fix below backend crash: |
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LGTM
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LGTM
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