arch-arm: Do not issue memory requests for uncacheable prefetches

[arichardson]

Currently, a prefetch instruction will result in an infinite sleep where
the CPU never wakes back up as it is expecting a dcache response even
though this will not be delivered for prefetches. Avoid this problem by
rejecting uncacheable prefetches in the MMU translation logic.

This allows my test workload from #1139
to continue running beyond strlen(). Tested using Atomic,Timing,Minor
and O3 CPU. See #1139 for the test
case that was used.

Fixes: #1139

Change-Id: Ic44bdb87f4099b11a7f9c6c99768a12fbef5842e

[ivanaamit]

Hi @arichardson, there are a couple of tests that are failing. Could you please fix that before this can be reviewed/merged? Thank you.

[giactra]

Hi @arichardson. Software prefetching has a hacky implementation in gem5 which makes it buggy in some cases.
I have already seen several PRs trying to put a patch on a specific problem without really solving the underlying issue.

While this PR fixes your run, I am afraid is not enough to fix SW prefetching properly. That would probably require to handle cpu,arch,mem-cache,mem-ruby implementation of SW prefetches at the same time.
For example in the PR you force the CPU into running but this is simply because the CPU never gets a prefetch response message. However, the gem5 CPU does require a response for the prefetch (even if in real CPUs it does not make sense) as you can see from the SoftPFReq definition:

/* SoftPFReq */
{ {IsRead, IsRequest, IsSWPrefetch, NeedsResponse},
        SoftPFResp, "SoftPFReq" },

So why does your CPU never gets a response? It does so because your data prefetch targets uncacheable data (as you can see from the debug log you posted). Therefore:

1. It should have never been issued in the first place
2. It never gets a dummy response from the cache: https://github.com/gem5/gem5/blob/stable/src/mem/cache/cache.cc#L380 (it is uncacheable)

So I believe a partial solution which would make things work for you would be related to point 1, which is: discard a SW prefetch if it targets uncacheable data as data won't be stored anyway...

[arichardson]

I believe I have a better fix for this now, scoped to the Arm MMU code. The new change allows my new reduced test case to pass for all CPU models.