arch-riscv: Fix viota instruction #1137
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This commit fixes and refactors the implementation of viota. It also overrides the generateDisassembly function in viota's macro/micro to correctly print out the instruction when tacing/debugging. For example, it changes from: viota_m vd, vd, vs2, v0.t to: viota_m vd, vs2, v0.t Change-Id: I6339a806db7c638f418533db57e44f4a76d609f9
hnpl
approved these changes
May 15, 2024
BobbyRBruce
approved these changes
May 20, 2024
BobbyRBruce
pushed a commit
to BobbyRBruce/gem5
that referenced
this pull request
May 25, 2024
This commit fixes and refactors the implementation of viota. It also overrides the generateDisassembly function in viota's macro/micro to correctly print out the instruction when tacing/debugging. For example, it changes from: viota_m vd, vd, vs2, v0.t to: viota_m vd, vs2, v0.t
BobbyRBruce
pushed a commit
to BobbyRBruce/gem5
that referenced
this pull request
Jun 7, 2024
This commit fixes and refactors the implementation of viota. It also overrides the generateDisassembly function in viota's macro/micro to correctly print out the instruction when tacing/debugging. For example, it changes from: viota_m vd, vd, vs2, v0.t to: viota_m vd, vs2, v0.t
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This commit fixes and refactors the implementation of viota. It also overrides the generateDisassembly function in viota's macro/micro to correctly print out the instruction when tacing/debugging.
For example, it changes from:
viota_m vd, vd, vs2, v0.t
to:
viota_m vd, vs2, v0.t
Change-Id: I6339a806db7c638f418533db57e44f4a76d609f9