-- Copyright 2017-2020 Frank Mori Hess fmh6jj@gmail.com

-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at

--    http://www.apache.org/licenses/LICENSE-2.0

-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.

-- See the LICENSE file for details.
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fmh_gpib_core is a GPIB IP core written in VHDL.  Currently, a
frontend with a cb7210.2 (NEC 7210) style register interface has been 
implemented (see src/frontends/frontend_cb7210p2.vhd) and tested in a
Cyclone V HPS clocked at 60 MHz.  fmh_gpib_core supports IEEE 488.1 
subsets SH1, SHE1, AH1, AHE1, T5, TE5, L3, LE3, SR1, RL1, PP0-PP2, DC1, DT1,
C1-C5, and CF.

The underlying GPIB logic is separated from the register interface 
so that multiple front end register layouts may be implemented on top
of the common core.

See src/example/fmh_gpib_top.vhd for an example of how the cb7210.2-style
frontend might be used.  It includes a fifo with a transfer counter to
accelerate DMA transfers and a digital filter for the GPIB control lines.
A corresponding component file usable by Altera's Quartus tools can be
found under vendor/altera/.

The latest version of this IP core may be found at:

https://github.com/fmhess/fmh_gpib_core

A linux driver for fmh_gpib_core is provided by the Linux-GPIB
package (the "fmh_gpib" driver), see: 

http://linux-gpib.sourceforge.net

The "nvc" VHDL compiler and simulator used to run the testbenches is 
available at https://github.com/nickg/nvc