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Apache 2.0 licensed copy of the Xilinx Unisim library.

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Xilinx Unisim Library

The Xilinx Unisim Library Verilog available as open source under Apache 2.0.

These files coincide with the 2020.1 release of Vivado.

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  • Verilog 97.8%
  • SystemVerilog 2.2%