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Core: Add a firewall framework + stm32 use case #6816

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Core: Add a firewall framework + stm32 use case #6816

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91e08bb
core: firewall: add firewall framework
GseoC May 2, 2024
7444de5
dt-bindings: add platform specific ETZPC bindings
GseoC May 2, 2024
41e91b6
dts: stm32: add the ETZPC configuration table for stm32mp1x boards
GseoC May 2, 2024
235e74b
drivers: stm32_etzpc: update driver to set ETZPC configuration from DT
GseoC May 2, 2024
ce324e9
dts: stm32: define ETZPC as an access controller for stm32mp15 boards
GseoC May 2, 2024
bdf7ebc
dts: stm32: define ETZPC as an access controller for stm32mp13 boards
GseoC May 2, 2024
348af97
plat-stm32mp1: default enable CFG_DRIVERS_FIREWALL
GseoC May 2, 2024
61ca178
drivers: stm32_etzpc: new driver to use firewall API
GseoC May 2, 2024
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27 changes: 24 additions & 3 deletions core/arch/arm/dts/stm32mp131.dtsi
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2021-2023 - All Rights Reserved
* Copyright (C) STMicroelectronics 2021-2024 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/

Expand All @@ -9,6 +9,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/regulator/st,stm32mp13-regulator.h>
#include <dt-bindings/reset/stm32mp13-resets.h>
#include <dt-bindings/soc/stm32mp13-etzpc.h>

/ {
#address-cells = <1>;
Expand Down Expand Up @@ -395,11 +396,12 @@
};

etzpc: etzpc@5c007000 {
compatible = "st,stm32-etzpc", "firewall-bus";
compatible = "st,stm32-etzpc", "simple-bus";
reg = <0x5C007000 0x400>;
clocks = <&rcc TZPC>;
#address-cells = <1>;
#size-cells = <1>;
#access-controller-cells = <2>;

adc_2: adc@48004000 {
reg = <0x48004000 0x400>;
Expand All @@ -411,6 +413,7 @@
#interrupt-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&etzpc STM32MP1_ETZPC_ADC2_ID 0>;
status = "disabled";

adc2: adc@0 {
Expand Down Expand Up @@ -451,6 +454,7 @@
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART1_K>;
resets = <&rcc USART1_R>;
access-controllers = <&etzpc STM32MP1_ETZPC_USART1_ID 0>;
status = "disabled";
};

Expand All @@ -460,6 +464,7 @@
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART2_K>;
resets = <&rcc USART2_R>;
access-controllers = <&etzpc STM32MP1_ETZPC_USART2_ID 0>;
status = "disabled";
};

Expand All @@ -472,6 +477,7 @@
#size-cells = <0>;
st,syscfg-fmp = <&syscfg 0x4 0x4>;
i2c-analog-filter;
access-controllers = <&etzpc STM32MP1_ETZPC_I2C3_ID 0>;
status = "disabled";
};

Expand All @@ -484,6 +490,7 @@
#size-cells = <0>;
st,syscfg-fmp = <&syscfg 0x4 0x8>;
i2c-analog-filter;
access-controllers = <&etzpc STM32MP1_ETZPC_I2C4_ID 0>;
status = "disabled";
};

Expand All @@ -496,6 +503,7 @@
#size-cells = <0>;
st,syscfg-fmp = <&syscfg 0x4 0x10>;
i2c-analog-filter;
access-controllers = <&etzpc STM32MP1_ETZPC_I2C5_ID 0>;
status = "disabled";
};

Expand All @@ -507,6 +515,8 @@
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc TIM12_K>;
clock-names = "int";
access-controllers = <&etzpc STM32MP1_ETZPC_TIM12_ID 0>;
status = "disabled";

counter {
compatible = "st,stm32-timer-counter";
Expand All @@ -521,6 +531,7 @@
reg = <0x4c008000 0x400>;
clocks = <&rcc TIM13_K>;
clock-names = "int";
access-controllers = <&etzpc STM32MP1_ETZPC_TIM13_ID 0>;
status = "disabled";
};

Expand All @@ -531,6 +542,7 @@
reg = <0x4c009000 0x400>;
clocks = <&rcc TIM14_K>;
clock-names = "int";
access-controllers = <&etzpc STM32MP1_ETZPC_TIM14_ID 0>;
status = "disabled";
};

Expand All @@ -542,6 +554,7 @@
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc TIM15_K>;
clock-names = "int";
access-controllers = <&etzpc STM32MP1_ETZPC_TIM15_ID 0>;
status = "disabled";

counter {
Expand All @@ -557,8 +570,8 @@
reg = <0x4c00b000 0x400>;
clocks = <&rcc TIM16_K>;
clock-names = "int";
access-controllers = <&etzpc STM32MP1_ETZPC_TIM16_ID 0>;
status = "disabled";

};

timers17: timer@4c00c000 {
Expand All @@ -568,6 +581,7 @@
reg = <0x4c00c000 0x400>;
clocks = <&rcc TIM17_K>;
clock-names = "int";
access-controllers = <&etzpc STM32MP1_ETZPC_TIM17_ID 0>;
status = "disabled";
};

Expand All @@ -579,6 +593,7 @@
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LPTIM2_K>;
clock-names = "mux";
access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM2_ID 0>;
status = "disabled";
};

Expand All @@ -590,6 +605,7 @@
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc LPTIM3_K>;
clock-names = "mux";
access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM3_ID 0>;
status = "disabled";

counter {
Expand All @@ -605,6 +621,7 @@
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <2500000>;
clocks = <&rcc VREF>;
access-controllers = <&etzpc STM32MP1_ETZPC_VREFBUF_ID 0>;
status = "disabled";
};

Expand All @@ -614,6 +631,7 @@
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc HASH1>;
resets = <&rcc HASH1_R>;
access-controllers = <&etzpc STM32MP1_ETZPC_HASH_ID 0>;
status = "disabled";
};

Expand All @@ -622,6 +640,7 @@
reg = <0x54004000 0x400>;
clocks = <&rcc RNG1_K>;
resets = <&rcc RNG1_R>;
access-controllers = <&etzpc STM32MP1_ETZPC_RNG_ID 0>;
status = "disabled";
};

Expand All @@ -631,12 +650,14 @@
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc IWDG1>, <&rcc CK_LSI>;
clock-names = "pclk", "lsi";
access-controllers = <&etzpc STM32MP1_ETZPC_IWDG1_ID 0>;
status = "disabled";
};

stgen: stgen@5c008000 {
compatible = "st,stm32-stgen";
reg = <0x5C008000 0x1000>;
access-controllers = <&etzpc STM32MP1_ETZPC_STGENC_ID 0>;
};
};
};
Expand Down
3 changes: 2 additions & 1 deletion core/arch/arm/dts/stm32mp135.dtsi
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2021-2022 - All Rights Reserved
* Copyright (C) STMicroelectronics 2021-2024 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/

Expand All @@ -17,6 +17,7 @@
clocks = <&rcc LTDC_PX>;
clock-names = "lcd";
resets = <&rcc LTDC_R>;
access-controllers = <&etzpc STM32MP1_ETZPC_LTDC_ID 0>;
status = "disabled";
};
};
Expand Down
48 changes: 47 additions & 1 deletion core/arch/arm/dts/stm32mp135f-dk.dts
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2021-2023 - All Rights Reserved
* Copyright (C) STMicroelectronics 2021-2024 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/

Expand Down Expand Up @@ -83,6 +83,52 @@
};
};

&etzpc {
st,decprot = <
DECPROT(STM32MP1_ETZPC_ADC1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_ADC2_ID, DECPROT_S_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_BKPSRAM_ID, DECPROT_S_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_CRYP_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_DCMIPP_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_DDRCTRLPHY_ID, DECPROT_NS_R_S_W, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_ETH1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_ETH2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_FMC_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_HASH_ID, DECPROT_S_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_I2C3_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_I2C4_ID, DECPROT_S_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_I2C5_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_IWDG1_ID, DECPROT_S_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_LPTIM2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_LPTIM3_ID, DECPROT_S_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_LTDC_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_MCE_ID, DECPROT_S_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_OTG_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_PKA_ID, DECPROT_S_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_QSPI_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_RNG_ID, DECPROT_S_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_SAES_ID, DECPROT_S_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_SDMMC1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_SDMMC2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_SPI4_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_SPI5_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_SRAM1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_SRAM2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_SRAM3_ID, DECPROT_S_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_STGENC_ID, DECPROT_S_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_TIM12_ID, DECPROT_S_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_TIM13_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_TIM14_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_TIM15_ID, DECPROT_S_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_TIM16_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_TIM17_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_USART1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_USART2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_USBPHYCTRL_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_VREFBUF_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
>;
};

&gpiob {
st,protreg = <TZPROT(9)>;
};
Expand Down
5 changes: 4 additions & 1 deletion core/arch/arm/dts/stm32mp13xc.dtsi
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2021-2022 - All Rights Reserved
* Copyright (C) STMicroelectronics 2021-2024 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/

Expand All @@ -11,6 +11,7 @@
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CRYP1>;
resets = <&rcc CRYP1_R>;
access-controllers = <&etzpc STM32MP1_ETZPC_SAES_ID 0>;
status = "disabled";
};

Expand All @@ -20,6 +21,7 @@
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc SAES_K>;
resets = <&rcc SAES_R>;
access-controllers = <&etzpc STM32MP1_ETZPC_SAES_ID 0>;
status = "disabled";
};

Expand All @@ -29,6 +31,7 @@
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc PKA>;
resets = <&rcc PKA_R>;
access-controllers = <&etzpc STM32MP1_ETZPC_PKA_ID 0>;
status = "disabled";
};
};
5 changes: 4 additions & 1 deletion core/arch/arm/dts/stm32mp13xf.dtsi
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2021-2022 - All Rights Reserved
* Copyright (C) STMicroelectronics 2021-2024 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/

Expand All @@ -11,6 +11,7 @@
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CRYP1>;
resets = <&rcc CRYP1_R>;
access-controllers = <&etzpc STM32MP1_ETZPC_CRYP_ID 0>;
status = "disabled";
};

Expand All @@ -20,6 +21,7 @@
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc SAES_K>;
resets = <&rcc SAES_R>;
access-controllers = <&etzpc STM32MP1_ETZPC_SAES_ID 0>;
status = "disabled";
};

Expand All @@ -29,6 +31,7 @@
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc PKA>;
resets = <&rcc PKA_R>;
access-controllers = <&etzpc STM32MP1_ETZPC_PKA_ID 0>;
status = "disabled";
};
};