Pinned

1. Tethorax Tethorax Public

   RISC V 32 bit Base ISA Implementation.

   VHDL 14 2

2. CS-polito CS-polito Public archive

   Solutions for the laboratory sessions of the first year undergraduate course "Computer Sciences" @ Politecnico di Torino

   Python 32 21

3. finjenv finjenv Public

   Fault injection environment (finjenv) of permanent hardware faults for various arithmetic circuits based on QuestaSIM logic simulator

   Verilog 1

4. cad-polito-it/r4ves cad-polito-it/r4ves Public

   RiscV Environment for Simulation (R4VES) is a generic and modular framework that eases the grunt work required in order to perform pre/post-synthesis logic and fault simulation on RISC-V cores base…

   Verilog 1 1

5. ksa ksa Public

   A synthesizable and modular Kogge-Stone Adder (KSA) implementation in SystemVerilog.

   SystemVerilog

6. LAP LAP Public

   Lark based DEF file parser

   Python 2 1