{"payload":{"header_redesign_enabled":false,"results":[{"id":"142230901","archived":false,"color":"#b2b7f8","followers":35,"has_funding_file":false,"hl_name":"vedic-partap/Computer-Organization-and-Architecture-LAB","hl_trunc_description":"Solution to COA LAB Assgn, IIT Kharagpur","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":142230901,"name":"Computer-Organization-and-Architecture-LAB","owner_id":23616128,"owner_login":"vedic-partap","updated_at":"2019-01-10T06:44:12.469Z","has_issues":true}},"sponsorable":false,"topics":["cpu","mips-assembly","verilog","hardware-designs","coa","verilog-project"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":60,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Avedic-partap%252FComputer-Organization-and-Architecture-LAB%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/vedic-partap/Computer-Organization-and-Architecture-LAB/star":{"post":"UN6Ey5HOK_ENpY6FltnMzc1o25LOXuzAPoQ-OQiQGwKtWx_Dtb-3Es-iQA6Z3DBCdBfcrLef9KuxdesUYP5rzA"},"/vedic-partap/Computer-Organization-and-Architecture-LAB/unstar":{"post":"vhjKRhMZ-dQI5tAmH5Xh-Bw1tbRvunGp4gqEoWfMi-EJ40oe2tzj8l4szdoKJgfxaF1-1YOc8LJhKgfMo94X8w"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"erMTV35cUf1EWVKw0nhP9U1o6AA2pdSYA_Axq-tawVdUWc0WOjs13owKp_Y7_ZPdLZ6XZPTmL5ocVDgS7LebfA"}}},"title":"Repository search results"}