An FPGA design for simulating biological neurons
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Updated
Jun 9, 2024 - SystemVerilog
An FPGA design for simulating biological neurons
It is a project on verilog which I had learned from a course taught by Prof. Indranil Sengupta at IIT Kharagpur.
I am trying to develop my skills through daily practice and consistency.
implementation of a basic computer having ability to perform logic and arithmetic operations
A verilog program that keeps count of the number of cars enter a parking lot and how many spots are free. Code made in Verilog for AMD FPGA xc7s50csga324-1 boolean board
Repository for RTL building blocks #100daysofrtl VERILOG VHDL System Verilog
Transformer Bitnet en Verilog
Exploring both MATLAB and Vivado Verilog in designing a Direct Digital Synthesizer (DDS) system with a FIR low-pass filter. This project goes into digital system design, signal processing, and hardware implementation.
A dump for my VHDL projects, because I want to have a better understanding of Verilog and also Logic circuits.
This Repository shows the implementation and results of various codes that I write in Verilog HDL
Router 1 x3 is a Basic level Design of Wireless Fidelity Router Model • The top level consists of 4 blocks-3 FIFO{First In First Out Register) , 1 Register, 1 Synchroniser and 1 Control Block (FSM-Finite State Machine) • RTL and Testbench are coded in verilog and the waveforms are generated using Modelsim software. • The Synthesis was performed u
In this project, I conducted an in-depth comparative analysis of various adder architectures to assess their performance in terms of delay and power consumption.
This project focuses on creating a hardware-based encryption and decryption system that implements the Data Encryption Standard (DES) algorithm.
This is an alarm clock made using Icarus Verilog as part of my Digital Design(DD) project.
During the EL-203 course, we had to make a elevator controller project under Professor Biswajit Mishra.
Traffic light controller for three way intersections
RISC-V single-cycle processor written in Verilog using the Quartus tool. Implementation of bubble sort through assembly language.
"Repository containing a collection of Verilog code modules and test bench for digital design projects. "
x and y are input signals representing the x and y coordinates, respectively, each being 1-bit wide.
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