DDR2 memory controller written in Verilog
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Updated
Feb 28, 2012 - Verilog
DDR2 memory controller written in Verilog
An 8 input interrupt controller written in Verilog.
This is the game "Brick Breaker" designed in verilog for an FPGA.
Display of various animated digital and analog clock using VGA control in FPGA
This repository contains all labs done as a part of the Embedded Logic and Design course.
Created Tank Wars using System Verilog for ECE385
RISC processor done in verilog hdl for FPGA
C- minus compiler for the Hydra microprocessor architecture
Title : Communication Bridge between I2C and SPI Platform : RTL Coding (Verilog/System Verilog/VHDL) Duration : 1 Month Description : Both SPI and I2C are robust, stable communication protocols that are widely used in today's complex systems.The I2C bus has a minimum pin count requirement and therefore a smaller footprint on the board. The SPI b…
FPGA based single player game
Transmitter and Receiver FPGAs connected using the UART Protocol to execute arithmetic operations and display the inputs on the transmitter's 7 Segment Display as well as the result on the Receiver's 7 Segments Display.
Verilog modules covering the single cycle processor
16 bit serial multiplier in SystemVerilog
This is a FPGA digital game using verilog to develop the frogger game
Design and Implementation of 5 stage pipeline architecture using verilog
Solution to COA LAB Assgn, IIT Kharagpur
BUAA Computer Organization Project4 CPU monocycle
BUAA Computer Organization Project5 CPU pipeline
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