testbench
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Project for the class "Digital Low-level Hardware Systems II" in SystemVerilog.
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Aug 30, 2022 - SystemVerilog
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Mar 14, 2023 - Python
Personal testbench for trying out stuff
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Apr 1, 2023 - Shell
Diseño de un circuito secuencial con entrada de datos x de 1 bit, una entrada de reset y una entrada de reloj. El sistema es un detector de secuencia que genera una salida z de 1 bit con ‘1’ cuando los últimos cuatro bits recibidos en x son 0101. El circuito se diseña de diversas maneras, cada una de ellas con una descripción en VHDL
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Sep 29, 2022 - VHDL
"Repository containing a collection of Verilog code modules and test bench for digital design projects. "
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Apr 1, 2024 - Verilog
A simple MIPS processor in Verilog.
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Jan 21, 2022 - Verilog
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Jun 3, 2024 - Verilog
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Nov 29, 2017 - Java
SCA on AVR testbench
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Sep 23, 2021 - Assembly
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Nov 29, 2017 - Java
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Aug 5, 2018 - HTML
bus interface, integrating LFSR’s for streamlined register management. Enabled seamless master-peripheral communication, enhancing system efficiency. Orchestrated comprehensive design stages, yielding a versatile RTL architecture for diverse applications
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May 28, 2024 - Verilog
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