sram
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ARM processor implementation, hazard unit, forwarding unit, SRAM & cache memory.
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Jul 24, 2023 - Verilog
A project built around learning new concepts and challenging my current understanding and capabilities in Firmware Development
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Jan 13, 2023 - C
Projects of the computer architecture lab (Spring 02) at the University of Tehran.
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Oct 6, 2023 - Verilog
uDMA is a template library for interfacing an Arduino with an external computer bus
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Aug 25, 2022 - C++
Using Altera FPGA (DE2-115) to finish 3 labs and 1 final project
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Sep 8, 2018 - SystemVerilog
For collaboration in ECSE 444
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Apr 13, 2019 - C
6T SRAM memory cell design and analysis using LTspice. Calculated noise margin, conducted Vdd scaling analysis, and analyzed Data Retention Voltage parameter for design optimization.
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Mar 26, 2024 - Python
Driver library for different components: LCD, LED controller, SRAMs.
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Apr 2, 2021 - C
This program is designated for testing the parallel SRAM/EEPROM chips with Arduino using the serial console as a command line interface.
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May 30, 2023 - C++
A cache controller implementation in VHDL for the demonstration of SRAM and SDRAM.
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May 6, 2022 - C
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