custom riscv embedded profile, replacing volume II (aka riscv privileged)
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Updated
May 28, 2024 - Makefile
Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
custom riscv embedded profile, replacing volume II (aka riscv privileged)
C++20 RISC-V RV32/64/128 userspace emulator library
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
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Compact and Efficient RISC-V RV32I[MAFC] emulator
CKB's vm, based on open source RISC-V ISA
ncnn is a high-performance neural network inference framework optimized for the mobile platform
Processador RISC-V multi ciclo com implementação RV32I construído em alguns dias de folga.
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
Методические материалы по разработке процессора архитектуры RISC-V