HF-RISC SoC
-
Updated
Jun 10, 2024 - C
HF-RISC SoC
C/C++ and NASM x86 compatable assembly language educational materials
SEA-M - Syntax-Encoding Assembler For MOOn-IV is a simple assembler for the MOOn-IV architecture. It is written in Python 3 and is a command-line tool.
Katamaran is a semi-automated separation logic verifier for the Sail specification language. It works on an embedded version of Sail called μSail and verifies separation logic-based contracts of functions by generating (succinct) first-order verification conditions.
DSM (Design Structure Matrix)
💻 An assembler for custom, user-defined instruction sets! https://hlorenzi.github.io/customasm/web/
Custom 32 bit computer
Rust implementation of AluVM (RISC functional machine)
a goofy 8 bit cpu
SAR: Simple Architecture RISC Simulator
Android MVVM Starter with Kotlin, Hilt, Coroutines, Retrofit2, Kotlin Flow, MockK, Espresso, JUnit4, and Jetpack Compose
RISC-V Assembly code assembler package for Python.
64-bit RISC CPU Architecture
Kite: Architecture Simulator for RISC-V Instruction Set
RISC V PROCESSOR DESIGN IN VERILOG
a small, fast and flexible assembler for risc-v assembly languange. currently it fully supports all the unpriviledged instructions of RV32M Instrution set
Database of CPU Opcodes
A simple CPU architecture specification based on AArch64 and with a little x86 inspiration. Additionally, a C implementation of this architecture and an assembler written in Python.
Add a description, image, and links to the instruction-set-architecture topic page so that developers can more easily learn about it.
To associate your repository with the instruction-set-architecture topic, visit your repo's landing page and select "manage topics."