Digital logic design tool and simulator

Digital logic gate simulator using React, TypeScript and p5.js

A modern hardware definition language and toolchain based on Python

This repository contains the Arduino code and schematic for a three-bit binary odd parity generator. The project uses 7400 series TTL to construct the parity generator.

This repository contains information about Digital Logic Design (ecen 3233) laboratory elements for Fall 2023.

This repo contains the EEL2020 course project, which was instructed to be made in hindi.

All codes Done during my Practical Session with Some Amazing Concepts

🎓💻All of my projects at University of Tehran

CSC302: Digital Logic Design and Analysis [DLDA] & CSL301: Digital System Lab [DS Lab] <Semester III>

This repository contains a vast collection of academic notes, study materials, and resources from various semesters of Datascience course.

Digital Electronics repo includes Boolean algebra and logic circuit design, covering topics such as gates, combinational and sequential circuits. It will help you learn logical circuit design principles, analyze circuits using automated tools, and delve into VHDL coding for the design and implementation of digital circuits on FPGA devices.

This repository contains all the academic projects made during the studies for the Bachelor's Degree in Engineering of Computing Systems and for the M.Sc. in Data Science.

Code collective of my 3rd Semester at ITER

Course Project for EE224 (Digital Systems) offered in Autumn 2023

A processor design using logism and verilog.

This repository contains data related to BS Computer Science

In our EEE283 Project, we're creating an automatic plant monitoring and irrigation system. Utilizing arithmetic, sequential, and combinational circuits.

We have developed an Electronic Voting Machine designed to tally the votes of 60 individuals. In this setup, there are six candidates vying for positions.

This project aims to create a network of logic gates that implements a simplified version of the standard algorithm for the histogram equalization method of an image, by recalibrating the contrast of an image when the range of intensity values is very close together.

converts a stg (.g file generated by workcraft) to a verilogA model