Benchmark of precision-scalable MAC unit architectures for embedded neural-network processing
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Updated
Dec 4, 2019
Benchmark of precision-scalable MAC unit architectures for embedded neural-network processing
Tiny Tapeout 04 Logic IC. Erics submission of his first real microchip doing basic safety chain control
Log visualizer for Whatsminer ASIC machines
Web-based map of the Gameboy DMG-CPU B with overlays
Hdl is a tool for easing the work with hardware description languages.
FIFO buffer library. Written and verified in SystemVerilog. Can be synthetised in ASIC or FPGA.
An application using Cadence IC Package
32 bit Risc-5 mimari işlemci tasarımı
This repository contains my BSc graduation project at the Faculty of Engineering, Ain Shams University. The project focuses on implementing the RISC-V core, specifically the CV32E40 ,with a focus on achieving high performance and maximizing frequency through synthesis, place and route (PNR).
A year before the first iPhone launched (2007), I worked on improving the robustness of WiFi chipsets for mobile devices using a data modulation technique called Orthogonal Frequency Division Multiplexing (OFDM). My main focus was developing a low power design for an OFDM core, which would minimize battery drain; thus avoiding the need for bigge…
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