An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
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Updated
Jun 12, 2024 - Scala
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Intel® Query Processing Library (Intel® QPL)
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.
Wrapper to accelerate linters like clang-tidy via ccache
HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing
Intel® Data Mover Library (Intel® DML)
Compile time kernels fusion and expression trees as Alpaka boost.odeint backend
CSV spreadsheets and other material for AI accelerator survey papers
SYCL for Vitis: Experimental fusion of triSYCL with Intel SYCL oneAPI DPC++ up-streaming effort into Clang/LLVM
[TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers
Fletcher: A framework to integrate FPGA accelerators with Apache Arrow
[TCAD'23] TransCODE: Co-design of Transformers and Accelerators for Efficient Training and Inference
A backend accelerator library supporting integrations to FICS for mortgage account and mortgage transaction details.
[TECS'23] A project on the co-design of Accelerators and CNNs.
Automatic virtualization of (general) accelerators.
A backend accelerator service supporting integrations with Centrix Positive Pay System
A backend accelerator library supporting integrations with Cardtronics to retrieve bank branch and ATM locations.
A backend accelerator library supporting integrations to Synergy for transaction check image and electronic statement retrieval.
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