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mac_be.c
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mac_be.c
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// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/* Copyright(c) 2019-2020 Realtek Corporation
*/
#include "debug.h"
#include "efuse.h"
#include "fw.h"
#include "mac.h"
#include "reg.h"
static const u32 rtw89_mac_mem_base_addrs_be[RTW89_MAC_MEM_NUM] = {
[RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR_BE,
[RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR_BE,
[RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR_BE,
[RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR_BE,
[RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR_BE,
[RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR_BE,
[RTW89_MAC_MEM_SECURITY_CAM] = SEC_CAM_BASE_ADDR_BE,
[RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR_BE,
[RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR_BE,
[RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR_BE,
[RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR_BE,
[RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR_BE,
[RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR_BE,
[RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR_BE,
[RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR_BE,
[RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR_BE,
[RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR_BE,
[RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR_BE,
[RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR_BE,
[RTW89_MAC_MEM_WD_PAGE] = WD_PAGE_BASE_ADDR_BE,
};
static const struct rtw89_port_reg rtw89_port_base_be = {
.port_cfg = R_BE_PORT_CFG_P0,
.tbtt_prohib = R_BE_TBTT_PROHIB_P0,
.bcn_area = R_BE_BCN_AREA_P0,
.bcn_early = R_BE_BCNERLYINT_CFG_P0,
.tbtt_early = R_BE_TBTTERLYINT_CFG_P0,
.tbtt_agg = R_BE_TBTT_AGG_P0,
.bcn_space = R_BE_BCN_SPACE_CFG_P0,
.bcn_forcetx = R_BE_BCN_FORCETX_P0,
.bcn_err_cnt = R_BE_BCN_ERR_CNT_P0,
.bcn_err_flag = R_BE_BCN_ERR_FLAG_P0,
.dtim_ctrl = R_BE_DTIM_CTRL_P0,
.tbtt_shift = R_BE_TBTT_SHIFT_P0,
.bcn_cnt_tmr = R_BE_BCN_CNT_TMR_P0,
.tsftr_l = R_BE_TSFTR_LOW_P0,
.tsftr_h = R_BE_TSFTR_HIGH_P0,
.md_tsft = R_BE_WMTX_MOREDATA_TSFT_STMP_CTL,
.bss_color = R_BE_PTCL_BSS_COLOR_0,
.mbssid = R_BE_MBSSID_CTRL,
.mbssid_drop = R_BE_MBSSID_DROP_0,
.tsf_sync = R_BE_PORT_0_TSF_SYNC,
.ptcl_dbg = R_BE_PTCL_DBG,
.ptcl_dbg_info = R_BE_PTCL_DBG_INFO,
.bcn_drop_all = R_BE_BCN_DROP_ALL0,
.hiq_win = {R_BE_P0MB_HGQ_WINDOW_CFG_0, R_BE_PORT_HGQ_WINDOW_CFG,
R_BE_PORT_HGQ_WINDOW_CFG + 1, R_BE_PORT_HGQ_WINDOW_CFG + 2,
R_BE_PORT_HGQ_WINDOW_CFG + 3},
};
static int rtw89_mac_check_mac_en_be(struct rtw89_dev *rtwdev, u8 mac_idx,
enum rtw89_mac_hwmod_sel sel)
{
if (sel == RTW89_DMAC_SEL &&
test_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags))
return 0;
if (sel == RTW89_CMAC_SEL && mac_idx == RTW89_MAC_0 &&
test_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags))
return 0;
if (sel == RTW89_CMAC_SEL && mac_idx == RTW89_MAC_1 &&
test_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags))
return 0;
return -EFAULT;
}
static bool is_qta_poh(struct rtw89_dev *rtwdev)
{
return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE;
}
static void hfc_get_mix_info_be(struct rtw89_dev *rtwdev)
{
struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg;
struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg;
struct rtw89_hfc_pub_info *info = ¶m->pub_info;
u32 val;
val = rtw89_read32(rtwdev, R_BE_PUB_PAGE_INFO1);
info->g0_used = u32_get_bits(val, B_BE_G0_USE_PG_MASK);
info->g1_used = u32_get_bits(val, B_BE_G1_USE_PG_MASK);
val = rtw89_read32(rtwdev, R_BE_PUB_PAGE_INFO3);
info->g0_aval = u32_get_bits(val, B_BE_G0_AVAL_PG_MASK);
info->g1_aval = u32_get_bits(val, B_BE_G1_AVAL_PG_MASK);
info->pub_aval = u32_get_bits(rtw89_read32(rtwdev, R_BE_PUB_PAGE_INFO2),
B_BE_PUB_AVAL_PG_MASK);
info->wp_aval = u32_get_bits(rtw89_read32(rtwdev, R_BE_WP_PAGE_INFO1),
B_BE_WP_AVAL_PG_MASK);
val = rtw89_read32(rtwdev, R_BE_HCI_FC_CTRL);
param->en = !!(val & B_BE_HCI_FC_EN);
param->h2c_en = !!(val & B_BE_HCI_FC_CH12_EN);
param->mode = u32_get_bits(val, B_BE_HCI_FC_MODE_MASK);
prec_cfg->ch011_full_cond = u32_get_bits(val, B_BE_HCI_FC_WD_FULL_COND_MASK);
prec_cfg->h2c_full_cond = u32_get_bits(val, B_BE_HCI_FC_CH12_FULL_COND_MASK);
prec_cfg->wp_ch07_full_cond =
u32_get_bits(val, B_BE_HCI_FC_WP_CH07_FULL_COND_MASK);
prec_cfg->wp_ch811_full_cond =
u32_get_bits(val, B_BE_HCI_FC_WP_CH811_FULL_COND_MASK);
val = rtw89_read32(rtwdev, R_BE_CH_PAGE_CTRL);
prec_cfg->ch011_prec = u32_get_bits(val, B_BE_PREC_PAGE_CH011_V1_MASK);
prec_cfg->h2c_prec = u32_get_bits(val, B_BE_PREC_PAGE_CH12_V1_MASK);
val = rtw89_read32(rtwdev, R_BE_PUB_PAGE_CTRL2);
pub_cfg->pub_max = u32_get_bits(val, B_BE_PUBPG_ALL_MASK);
val = rtw89_read32(rtwdev, R_BE_WP_PAGE_CTRL1);
prec_cfg->wp_ch07_prec = u32_get_bits(val, B_BE_PREC_PAGE_WP_CH07_MASK);
prec_cfg->wp_ch811_prec = u32_get_bits(val, B_BE_PREC_PAGE_WP_CH811_MASK);
val = rtw89_read32(rtwdev, R_BE_WP_PAGE_CTRL2);
pub_cfg->wp_thrd = u32_get_bits(val, B_BE_WP_THRD_MASK);
val = rtw89_read32(rtwdev, R_BE_PUB_PAGE_CTRL1);
pub_cfg->grp0 = u32_get_bits(val, B_BE_PUBPG_G0_MASK);
pub_cfg->grp1 = u32_get_bits(val, B_BE_PUBPG_G1_MASK);
}
static void hfc_h2c_cfg_be(struct rtw89_dev *rtwdev)
{
struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg;
u32 val;
val = u32_encode_bits(prec_cfg->h2c_prec, B_BE_PREC_PAGE_CH12_V1_MASK);
rtw89_write32(rtwdev, R_BE_CH_PAGE_CTRL, val);
}
static void hfc_mix_cfg_be(struct rtw89_dev *rtwdev)
{
struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg;
const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg;
u32 val;
val = u32_encode_bits(prec_cfg->ch011_prec, B_BE_PREC_PAGE_CH011_V1_MASK) |
u32_encode_bits(prec_cfg->h2c_prec, B_BE_PREC_PAGE_CH12_V1_MASK);
rtw89_write32(rtwdev, R_BE_CH_PAGE_CTRL, val);
val = u32_encode_bits(pub_cfg->pub_max, B_BE_PUBPG_ALL_MASK);
rtw89_write32(rtwdev, R_BE_PUB_PAGE_CTRL2, val);
val = u32_encode_bits(prec_cfg->wp_ch07_prec, B_BE_PREC_PAGE_WP_CH07_MASK) |
u32_encode_bits(prec_cfg->wp_ch811_prec, B_BE_PREC_PAGE_WP_CH811_MASK);
rtw89_write32(rtwdev, R_BE_WP_PAGE_CTRL1, val);
val = u32_replace_bits(rtw89_read32(rtwdev, R_BE_HCI_FC_CTRL),
param->mode, B_BE_HCI_FC_MODE_MASK);
val = u32_replace_bits(val, prec_cfg->ch011_full_cond,
B_BE_HCI_FC_WD_FULL_COND_MASK);
val = u32_replace_bits(val, prec_cfg->h2c_full_cond,
B_BE_HCI_FC_CH12_FULL_COND_MASK);
val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond,
B_BE_HCI_FC_WP_CH07_FULL_COND_MASK);
val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond,
B_BE_HCI_FC_WP_CH811_FULL_COND_MASK);
rtw89_write32(rtwdev, R_BE_HCI_FC_CTRL, val);
}
static void hfc_func_en_be(struct rtw89_dev *rtwdev, bool en, bool h2c_en)
{
struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
u32 val;
val = rtw89_read32(rtwdev, R_BE_HCI_FC_CTRL);
param->en = en;
param->h2c_en = h2c_en;
val = en ? (val | B_BE_HCI_FC_EN) : (val & ~B_BE_HCI_FC_EN);
val = h2c_en ? (val | B_BE_HCI_FC_CH12_EN) :
(val & ~B_BE_HCI_FC_CH12_EN);
rtw89_write32(rtwdev, R_BE_HCI_FC_CTRL, val);
}
static void dle_func_en_be(struct rtw89_dev *rtwdev, bool enable)
{
if (enable)
rtw89_write32_set(rtwdev, R_BE_DMAC_FUNC_EN,
B_BE_DLE_WDE_EN | B_BE_DLE_PLE_EN);
else
rtw89_write32_clr(rtwdev, R_BE_DMAC_FUNC_EN,
B_BE_DLE_WDE_EN | B_BE_DLE_PLE_EN);
}
static void dle_clk_en_be(struct rtw89_dev *rtwdev, bool enable)
{
if (enable)
rtw89_write32_set(rtwdev, R_BE_DMAC_CLK_EN,
B_BE_DLE_WDE_CLK_EN | B_BE_DLE_PLE_CLK_EN);
else
rtw89_write32_clr(rtwdev, R_BE_DMAC_CLK_EN,
B_BE_DLE_WDE_CLK_EN | B_BE_DLE_PLE_CLK_EN);
}
static int dle_mix_cfg_be(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg)
{
const struct rtw89_dle_size *wde_size_cfg, *ple_size_cfg;
u32 bound;
u32 val;
wde_size_cfg = cfg->wde_size;
ple_size_cfg = cfg->ple_size;
val = rtw89_read32(rtwdev, R_BE_WDE_PKTBUF_CFG);
switch (wde_size_cfg->pge_size) {
default:
case RTW89_WDE_PG_64:
val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64,
B_BE_WDE_PAGE_SEL_MASK);
break;
case RTW89_WDE_PG_128:
val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128,
B_BE_WDE_PAGE_SEL_MASK);
break;
case RTW89_WDE_PG_256:
rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n");
return -EINVAL;
}
bound = wde_size_cfg->srt_ofst / DLE_BOUND_UNIT;
val = u32_replace_bits(val, bound, B_BE_WDE_START_BOUND_MASK);
val = u32_replace_bits(val, wde_size_cfg->lnk_pge_num,
B_BE_WDE_FREE_PAGE_NUM_MASK);
rtw89_write32(rtwdev, R_BE_WDE_PKTBUF_CFG, val);
val = rtw89_read32(rtwdev, R_BE_PLE_PKTBUF_CFG);
switch (ple_size_cfg->pge_size) {
default:
case RTW89_PLE_PG_64:
rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n");
return -EINVAL;
case RTW89_PLE_PG_128:
val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128,
B_BE_PLE_PAGE_SEL_MASK);
break;
case RTW89_PLE_PG_256:
val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256,
B_BE_PLE_PAGE_SEL_MASK);
break;
}
bound = ple_size_cfg->srt_ofst / DLE_BOUND_UNIT;
val = u32_replace_bits(val, bound, B_BE_PLE_START_BOUND_MASK);
val = u32_replace_bits(val, ple_size_cfg->lnk_pge_num,
B_BE_PLE_FREE_PAGE_NUM_MASK);
rtw89_write32(rtwdev, R_BE_PLE_PKTBUF_CFG, val);
return 0;
}
static int chk_dle_rdy_be(struct rtw89_dev *rtwdev, bool wde_or_ple)
{
u32 reg, mask;
u32 ini;
if (wde_or_ple) {
reg = R_AX_WDE_INI_STATUS;
mask = WDE_MGN_INI_RDY;
} else {
reg = R_AX_PLE_INI_STATUS;
mask = PLE_MGN_INI_RDY;
}
return read_poll_timeout(rtw89_read32, ini, (ini & mask) == mask, 1,
2000, false, rtwdev, reg);
}
#define INVALID_QT_WCPU U16_MAX
#define SET_QUOTA_VAL(_min_x, _max_x, _module, _idx) \
do { \
val = u32_encode_bits(_min_x, B_BE_ ## _module ## _Q ## _idx ## _MIN_SIZE_MASK) | \
u32_encode_bits(_max_x, B_BE_ ## _module ## _Q ## _idx ## _MAX_SIZE_MASK); \
rtw89_write32(rtwdev, \
R_BE_ ## _module ## _QTA ## _idx ## _CFG, \
val); \
} while (0)
#define SET_QUOTA(_x, _module, _idx) \
SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx)
static void wde_quota_cfg_be(struct rtw89_dev *rtwdev,
const struct rtw89_wde_quota *min_cfg,
const struct rtw89_wde_quota *max_cfg,
u16 ext_wde_min_qt_wcpu)
{
u16 min_qt_wcpu = ext_wde_min_qt_wcpu != INVALID_QT_WCPU ?
ext_wde_min_qt_wcpu : min_cfg->wcpu;
u16 max_qt_wcpu = max(max_cfg->wcpu, min_qt_wcpu);
u32 val;
SET_QUOTA(hif, WDE, 0);
SET_QUOTA_VAL(min_qt_wcpu, max_qt_wcpu, WDE, 1);
SET_QUOTA_VAL(0, 0, WDE, 2);
SET_QUOTA(pkt_in, WDE, 3);
SET_QUOTA(cpu_io, WDE, 4);
}
static void ple_quota_cfg_be(struct rtw89_dev *rtwdev,
const struct rtw89_ple_quota *min_cfg,
const struct rtw89_ple_quota *max_cfg)
{
u32 val;
SET_QUOTA(cma0_tx, PLE, 0);
SET_QUOTA(cma1_tx, PLE, 1);
SET_QUOTA(c2h, PLE, 2);
SET_QUOTA(h2c, PLE, 3);
SET_QUOTA(wcpu, PLE, 4);
SET_QUOTA(mpdu_proc, PLE, 5);
SET_QUOTA(cma0_dma, PLE, 6);
SET_QUOTA(cma1_dma, PLE, 7);
SET_QUOTA(bb_rpt, PLE, 8);
SET_QUOTA(wd_rel, PLE, 9);
SET_QUOTA(cpu_io, PLE, 10);
SET_QUOTA(tx_rpt, PLE, 11);
SET_QUOTA(h2d, PLE, 12);
}
static void rtw89_mac_hci_func_en_be(struct rtw89_dev *rtwdev)
{
rtw89_write32_set(rtwdev, R_BE_HCI_FUNC_EN, B_BE_HCI_TXDMA_EN |
B_BE_HCI_RXDMA_EN);
}
static void rtw89_mac_dmac_func_pre_en_be(struct rtw89_dev *rtwdev)
{
u32 val;
val = rtw89_read32(rtwdev, R_BE_HAXI_INIT_CFG1);
switch (rtwdev->hci.type) {
case RTW89_HCI_TYPE_PCIE:
val = u32_replace_bits(val, S_BE_DMA_MOD_PCIE_NO_DATA_CPU,
B_BE_DMA_MODE_MASK);
break;
case RTW89_HCI_TYPE_USB:
val = u32_replace_bits(val, S_BE_DMA_MOD_USB, B_BE_DMA_MODE_MASK);
val = (val & ~B_BE_STOP_AXI_MST) | B_BE_TXDMA_EN | B_BE_RXDMA_EN;
break;
case RTW89_HCI_TYPE_SDIO:
val = u32_replace_bits(val, S_BE_DMA_MOD_SDIO, B_BE_DMA_MODE_MASK);
val = (val & ~B_BE_STOP_AXI_MST) | B_BE_TXDMA_EN | B_BE_RXDMA_EN;
break;
default:
return;
}
rtw89_write32(rtwdev, R_BE_HAXI_INIT_CFG1, val);
rtw89_write32_clr(rtwdev, R_BE_HAXI_DMA_STOP1,
B_BE_STOP_CH0 | B_BE_STOP_CH1 | B_BE_STOP_CH2 |
B_BE_STOP_CH3 | B_BE_STOP_CH4 | B_BE_STOP_CH5 |
B_BE_STOP_CH6 | B_BE_STOP_CH7 | B_BE_STOP_CH8 |
B_BE_STOP_CH9 | B_BE_STOP_CH10 | B_BE_STOP_CH11 |
B_BE_STOP_CH12 | B_BE_STOP_CH13 | B_BE_STOP_CH14);
rtw89_write32_set(rtwdev, R_BE_DMAC_TABLE_CTRL, B_BE_DMAC_ADDR_MODE);
}
static
int rtw89_mac_write_xtal_si_be(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask)
{
u32 val32;
int ret;
val32 = u32_encode_bits(offset, B_BE_WL_XTAL_SI_ADDR_MASK) |
u32_encode_bits(val, B_BE_WL_XTAL_SI_DATA_MASK) |
u32_encode_bits(mask, B_BE_WL_XTAL_SI_BITMASK_MASK) |
u32_encode_bits(XTAL_SI_NORMAL_WRITE, B_BE_WL_XTAL_SI_MODE_MASK) |
u32_encode_bits(0, B_BE_WL_XTAL_SI_CHIPID_MASK) |
B_BE_WL_XTAL_SI_CMD_POLL;
rtw89_write32(rtwdev, R_BE_WLAN_XTAL_SI_CTRL, val32);
ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_BE_WL_XTAL_SI_CMD_POLL),
50, 50000, false, rtwdev, R_BE_WLAN_XTAL_SI_CTRL);
if (ret) {
rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n",
offset, val, mask);
return ret;
}
return 0;
}
static
int rtw89_mac_read_xtal_si_be(struct rtw89_dev *rtwdev, u8 offset, u8 *val)
{
u32 val32;
int ret;
val32 = u32_encode_bits(offset, B_BE_WL_XTAL_SI_ADDR_MASK) |
u32_encode_bits(0x0, B_BE_WL_XTAL_SI_DATA_MASK) |
u32_encode_bits(0x0, B_BE_WL_XTAL_SI_BITMASK_MASK) |
u32_encode_bits(XTAL_SI_NORMAL_READ, B_BE_WL_XTAL_SI_MODE_MASK) |
u32_encode_bits(0, B_BE_WL_XTAL_SI_CHIPID_MASK) |
B_BE_WL_XTAL_SI_CMD_POLL;
rtw89_write32(rtwdev, R_BE_WLAN_XTAL_SI_CTRL, val32);
ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_BE_WL_XTAL_SI_CMD_POLL),
50, 50000, false, rtwdev, R_BE_WLAN_XTAL_SI_CTRL);
if (ret) {
rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset);
return ret;
}
*val = rtw89_read8(rtwdev, R_BE_WLAN_XTAL_SI_CTRL + 1);
return 0;
}
static void rtw89_mac_disable_cpu_be(struct rtw89_dev *rtwdev)
{
u32 val32;
clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags);
rtw89_write32_clr(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_WCPU_EN);
rtw89_write32_set(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_HOLD_AFTER_RESET);
rtw89_write32_set(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_WCPU_EN);
val32 = rtw89_read32(rtwdev, R_BE_WCPU_FW_CTRL);
val32 &= B_BE_RUN_ENV_MASK;
rtw89_write32(rtwdev, R_BE_WCPU_FW_CTRL, val32);
rtw89_write32_set(rtwdev, R_BE_DCPU_PLATFORM_ENABLE, B_BE_DCPU_PLATFORM_EN);
rtw89_write32(rtwdev, R_BE_UDM0, 0);
rtw89_write32(rtwdev, R_BE_HALT_C2H, 0);
rtw89_write32(rtwdev, R_BE_UDM2, 0);
}
static void set_cpu_en(struct rtw89_dev *rtwdev, bool include_bb)
{
u32 set = B_BE_WLANCPU_FWDL_EN;
if (include_bb)
set |= B_BE_BBMCU0_FWDL_EN;
rtw89_write32_set(rtwdev, R_BE_WCPU_FW_CTRL, set);
}
static int wcpu_on(struct rtw89_dev *rtwdev, u8 boot_reason, bool dlfw)
{
u32 val32;
int ret;
val32 = rtw89_read32(rtwdev, R_BE_HALT_C2H);
if (val32) {
rtw89_warn(rtwdev, "[SER] AON L2 Debug register not empty before Boot.\n");
rtw89_warn(rtwdev, "[SER] %s: R_BE_HALT_C2H = 0x%x\n", __func__, val32);
}
val32 = rtw89_read32(rtwdev, R_BE_UDM1);
if (val32) {
rtw89_warn(rtwdev, "[SER] AON L2 Debug register not empty before Boot.\n");
rtw89_warn(rtwdev, "[SER] %s: R_BE_UDM1 = 0x%x\n", __func__, val32);
}
val32 = rtw89_read32(rtwdev, R_BE_UDM2);
if (val32) {
rtw89_warn(rtwdev, "[SER] AON L2 Debug register not empty before Boot.\n");
rtw89_warn(rtwdev, "[SER] %s: R_BE_UDM2 = 0x%x\n", __func__, val32);
}
rtw89_write32(rtwdev, R_BE_UDM1, 0);
rtw89_write32(rtwdev, R_BE_UDM2, 0);
rtw89_write32(rtwdev, R_BE_HALT_H2C, 0);
rtw89_write32(rtwdev, R_BE_HALT_C2H, 0);
rtw89_write32(rtwdev, R_BE_HALT_H2C_CTRL, 0);
rtw89_write32(rtwdev, R_BE_HALT_C2H_CTRL, 0);
val32 = rtw89_read32(rtwdev, R_BE_HISR0);
rtw89_write32(rtwdev, R_BE_HISR0, B_BE_HALT_C2H_INT);
rtw89_debug(rtwdev, RTW89_DBG_SER, "HISR0=0x%x\n", val32);
rtw89_write32_set(rtwdev, R_BE_SYS_CLK_CTRL, B_BE_CPU_CLK_EN);
rtw89_write32_clr(rtwdev, R_BE_SYS_CFG5,
B_BE_WDT_WAKE_PCIE_EN | B_BE_WDT_WAKE_USB_EN);
rtw89_write32_clr(rtwdev, R_BE_WCPU_FW_CTRL,
B_BE_WDT_PLT_RST_EN | B_BE_WCPU_ROM_CUT_GET);
rtw89_write16_mask(rtwdev, R_BE_BOOT_REASON, B_BE_BOOT_REASON_MASK, boot_reason);
rtw89_write32_clr(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_WCPU_EN);
rtw89_write32_clr(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_HOLD_AFTER_RESET);
rtw89_write32_set(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_WCPU_EN);
if (!dlfw) {
ret = rtw89_fw_check_rdy(rtwdev, RTW89_FWDL_CHECK_FREERTOS_DONE);
if (ret)
return ret;
}
return 0;
}
static int rtw89_mac_fwdl_enable_wcpu_be(struct rtw89_dev *rtwdev,
u8 boot_reason, bool dlfw,
bool include_bb)
{
set_cpu_en(rtwdev, include_bb);
return wcpu_on(rtwdev, boot_reason, dlfw);
}
static const u8 fwdl_status_map[] = {
[0] = RTW89_FWDL_INITIAL_STATE,
[1] = RTW89_FWDL_FWDL_ONGOING,
[4] = RTW89_FWDL_CHECKSUM_FAIL,
[5] = RTW89_FWDL_SECURITY_FAIL,
[6] = RTW89_FWDL_SECURITY_FAIL,
[7] = RTW89_FWDL_CV_NOT_MATCH,
[8] = RTW89_FWDL_RSVD0,
[2] = RTW89_FWDL_WCPU_FWDL_RDY,
[3] = RTW89_FWDL_WCPU_FW_INIT_RDY,
[9] = RTW89_FWDL_RSVD0,
};
static u8 fwdl_get_status_be(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type)
{
bool check_pass = false;
u32 val32;
u8 st;
val32 = rtw89_read32(rtwdev, R_BE_WCPU_FW_CTRL);
switch (type) {
case RTW89_FWDL_CHECK_WCPU_FWDL_DONE:
check_pass = !(val32 & B_BE_WLANCPU_FWDL_EN);
break;
case RTW89_FWDL_CHECK_DCPU_FWDL_DONE:
check_pass = !(val32 & B_BE_DATACPU_FWDL_EN);
break;
case RTW89_FWDL_CHECK_BB0_FWDL_DONE:
check_pass = !(val32 & B_BE_BBMCU0_FWDL_EN);
break;
case RTW89_FWDL_CHECK_BB1_FWDL_DONE:
check_pass = !(val32 & B_BE_BBMCU1_FWDL_EN);
break;
default:
break;
}
if (check_pass)
return RTW89_FWDL_WCPU_FW_INIT_RDY;
st = u32_get_bits(val32, B_BE_WCPU_FWDL_STATUS_MASK);
if (st < ARRAY_SIZE(fwdl_status_map))
return fwdl_status_map[st];
return st;
}
static int rtw89_fwdl_check_path_ready_be(struct rtw89_dev *rtwdev,
bool h2c_or_fwdl)
{
u32 check = h2c_or_fwdl ? B_BE_H2C_PATH_RDY : B_BE_DLFW_PATH_RDY;
u32 val;
return read_poll_timeout_atomic(rtw89_read32, val, val & check,
1, 1000000, false,
rtwdev, R_BE_WCPU_FW_CTRL);
}
static int dmac_func_en_be(struct rtw89_dev *rtwdev)
{
return 0;
}
static int cmac_func_en_be(struct rtw89_dev *rtwdev, u8 mac_idx, bool en)
{
u32 reg;
if (mac_idx > RTW89_MAC_1)
return -EINVAL;
if (mac_idx == RTW89_MAC_0)
return 0;
if (en) {
rtw89_write32_set(rtwdev, R_BE_AFE_CTRL1, B_BE_AFE_CTRL1_SET);
rtw89_write32_clr(rtwdev, R_BE_SYS_ISO_CTRL_EXTEND, B_BE_R_SYM_ISO_CMAC12PP);
rtw89_write32_set(rtwdev, R_BE_FEN_RST_ENABLE, B_BE_CMAC1_FEN);
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CK_EN, mac_idx);
rtw89_write32_set(rtwdev, reg, B_BE_CK_EN_SET);
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CMAC_FUNC_EN, mac_idx);
rtw89_write32_set(rtwdev, reg, B_BE_CMAC_FUNC_EN_SET);
set_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags);
} else {
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CMAC_FUNC_EN, mac_idx);
rtw89_write32_clr(rtwdev, reg, B_BE_CMAC_FUNC_EN_SET);
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CK_EN, mac_idx);
rtw89_write32_clr(rtwdev, reg, B_BE_CK_EN_SET);
rtw89_write32_clr(rtwdev, R_BE_FEN_RST_ENABLE, B_BE_CMAC1_FEN);
rtw89_write32_set(rtwdev, R_BE_SYS_ISO_CTRL_EXTEND, B_BE_R_SYM_ISO_CMAC12PP);
rtw89_write32_clr(rtwdev, R_BE_AFE_CTRL1, B_BE_AFE_CTRL1_SET);
clear_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags);
}
return 0;
}
static int chip_func_en_be(struct rtw89_dev *rtwdev)
{
return 0;
}
static int sys_init_be(struct rtw89_dev *rtwdev)
{
int ret;
ret = dmac_func_en_be(rtwdev);
if (ret)
return ret;
ret = cmac_func_en_be(rtwdev, RTW89_MAC_0, true);
if (ret)
return ret;
ret = chip_func_en_be(rtwdev);
if (ret)
return ret;
return ret;
}
static int sta_sch_init_be(struct rtw89_dev *rtwdev)
{
u32 p_val;
int ret;
ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
if (ret)
return ret;
rtw89_write8_set(rtwdev, R_BE_SS_CTRL, B_BE_SS_EN);
ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_BE_SS_INIT_DONE,
1, TRXCFG_WAIT_CNT, false, rtwdev, R_BE_SS_CTRL);
if (ret) {
rtw89_err(rtwdev, "[ERR]STA scheduler init\n");
return ret;
}
rtw89_write32_set(rtwdev, R_BE_SS_CTRL, B_BE_WARM_INIT);
rtw89_write32_clr(rtwdev, R_BE_SS_CTRL, B_BE_BAND_TRIG_EN | B_BE_BAND1_TRIG_EN);
return 0;
}
static int mpdu_proc_init_be(struct rtw89_dev *rtwdev)
{
u32 val32;
int ret;
ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
if (ret)
return ret;
rtw89_write32_set(rtwdev, R_BE_MPDU_PROC, B_BE_APPEND_FCS);
rtw89_write32(rtwdev, R_BE_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL);
val32 = rtw89_read32(rtwdev, R_BE_HDR_SHCUT_SETTING);
val32 |= (B_BE_TX_HW_SEQ_EN | B_BE_TX_HW_ACK_POLICY_EN | B_BE_TX_MAC_MPDU_PROC_EN);
val32 &= ~B_BE_TX_ADDR_MLD_TO_LIK;
rtw89_write32_set(rtwdev, R_BE_HDR_SHCUT_SETTING, val32);
rtw89_write32(rtwdev, R_BE_RX_HDRTRNS, TRXCFG_MPDU_PROC_RX_HDR_CONV);
val32 = rtw89_read32(rtwdev, R_BE_DISP_FWD_WLAN_0);
val32 = u32_replace_bits(val32, 1, B_BE_FWD_WLAN_CPU_TYPE_0_DATA_MASK);
val32 = u32_replace_bits(val32, 1, B_BE_FWD_WLAN_CPU_TYPE_0_MNG_MASK);
val32 = u32_replace_bits(val32, 1, B_BE_FWD_WLAN_CPU_TYPE_0_CTL_MASK);
val32 = u32_replace_bits(val32, 1, B_BE_FWD_WLAN_CPU_TYPE_1_MASK);
rtw89_write32(rtwdev, R_BE_DISP_FWD_WLAN_0, val32);
return 0;
}
static int sec_eng_init_be(struct rtw89_dev *rtwdev)
{
u32 val32;
int ret;
ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
if (ret)
return ret;
val32 = rtw89_read32(rtwdev, R_BE_SEC_ENG_CTRL);
val32 |= B_BE_CLK_EN_CGCMP | B_BE_CLK_EN_WAPI | B_BE_CLK_EN_WEP_TKIP |
B_BE_SEC_TX_ENC | B_BE_SEC_RX_DEC |
B_BE_MC_DEC | B_BE_BC_DEC |
B_BE_BMC_MGNT_DEC | B_BE_UC_MGNT_DEC;
val32 &= ~B_BE_SEC_PRE_ENQUE_TX;
rtw89_write32(rtwdev, R_BE_SEC_ENG_CTRL, val32);
rtw89_write32_set(rtwdev, R_BE_SEC_MPDU_PROC, B_BE_APPEND_ICV | B_BE_APPEND_MIC);
return 0;
}
static int txpktctrl_init_be(struct rtw89_dev *rtwdev)
{
struct rtw89_mac_dle_rsvd_qt_cfg qt_cfg;
u32 val32;
int ret;
ret = rtw89_mac_get_dle_rsvd_qt_cfg(rtwdev, DLE_RSVD_QT_MPDU_INFO, &qt_cfg);
if (ret) {
rtw89_err(rtwdev, "get dle rsvd qt %d cfg fail %d\n",
DLE_RSVD_QT_MPDU_INFO, ret);
return ret;
}
val32 = rtw89_read32(rtwdev, R_BE_TXPKTCTL_MPDUINFO_CFG);
val32 = u32_replace_bits(val32, qt_cfg.pktid, B_BE_MPDUINFO_PKTID_MASK);
val32 = u32_replace_bits(val32, MPDU_INFO_B1_OFST, B_BE_MPDUINFO_B1_BADDR_MASK);
val32 |= B_BE_MPDUINFO_FEN;
rtw89_write32(rtwdev, R_BE_TXPKTCTL_MPDUINFO_CFG, val32);
return 0;
}
static int mlo_init_be(struct rtw89_dev *rtwdev)
{
u32 val32;
int ret;
val32 = rtw89_read32(rtwdev, R_BE_MLO_INIT_CTL);
val32 |= B_BE_MLO_TABLE_REINIT;
rtw89_write32(rtwdev, R_BE_MLO_INIT_CTL, val32);
val32 &= ~B_BE_MLO_TABLE_REINIT;
rtw89_write32(rtwdev, R_BE_MLO_INIT_CTL, val32);
ret = read_poll_timeout_atomic(rtw89_read32, val32,
val32 & B_BE_MLO_TABLE_INIT_DONE,
1, 1000, false, rtwdev, R_BE_MLO_INIT_CTL);
if (ret)
rtw89_err(rtwdev, "[MLO]%s: MLO init polling timeout\n", __func__);
rtw89_write32_set(rtwdev, R_BE_SS_CTRL, B_BE_MLO_HW_CHGLINK_EN);
rtw89_write32_set(rtwdev, R_BE_CMAC_SHARE_ACQCHK_CFG_0, B_BE_R_MACID_ACQ_CHK_EN);
return ret;
}
static int dmac_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
{
int ret;
ret = rtw89_mac_dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID);
if (ret) {
rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret);
return ret;
}
ret = rtw89_mac_preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode);
if (ret) {
rtw89_err(rtwdev, "[ERR]preload init %d\n", ret);
return ret;
}
ret = rtw89_mac_hfc_init(rtwdev, true, true, true);
if (ret) {
rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret);
return ret;
}
ret = sta_sch_init_be(rtwdev);
if (ret) {
rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret);
return ret;
}
ret = mpdu_proc_init_be(rtwdev);
if (ret) {
rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret);
return ret;
}
ret = sec_eng_init_be(rtwdev);
if (ret) {
rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret);
return ret;
}
ret = txpktctrl_init_be(rtwdev);
if (ret) {
rtw89_err(rtwdev, "[ERR]TX pkt ctrl init %d\n", ret);
return ret;
}
ret = mlo_init_be(rtwdev);
if (ret) {
rtw89_err(rtwdev, "[ERR]MLO init %d\n", ret);
return ret;
}
return ret;
}
static int scheduler_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
{
u32 val32;
u32 reg;
int ret;
ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
if (ret)
return ret;
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_HE_CTN_CHK_CCA_NAV, mac_idx);
val32 = B_BE_HE_CTN_CHK_CCA_P20 | B_BE_HE_CTN_CHK_EDCCA_P20 |
B_BE_HE_CTN_CHK_CCA_BITMAP | B_BE_HE_CTN_CHK_EDCCA_BITMAP |
B_BE_HE_CTN_CHK_NO_GNT_WL | B_BE_HE_CTN_CHK_BASIC_NAV |
B_BE_HE_CTN_CHK_INTRA_NAV | B_BE_HE_CTN_CHK_TX_NAV;
rtw89_write32(rtwdev, reg, val32);
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_HE_SIFS_CHK_CCA_NAV, mac_idx);
val32 = B_BE_HE_SIFS_CHK_EDCCA_P20 | B_BE_HE_SIFS_CHK_EDCCA_BITMAP |
B_BE_HE_SIFS_CHK_NO_GNT_WL;
rtw89_write32(rtwdev, reg, val32);
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TB_CHK_CCA_NAV, mac_idx);
val32 = B_BE_TB_CHK_EDCCA_BITMAP | B_BE_TB_CHK_NO_GNT_WL | B_BE_TB_CHK_BASIC_NAV;
rtw89_write32(rtwdev, reg, val32);
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CCA_CFG_0, mac_idx);
rtw89_write32_clr(rtwdev, reg, B_BE_NO_GNT_WL_EN);
if (is_qta_poh(rtwdev)) {
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PREBKF_CFG_0, mac_idx);
rtw89_write32_mask(rtwdev, reg, B_BE_PREBKF_TIME_MASK,
SCH_PREBKF_24US);
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CTN_CFG_0, mac_idx);
rtw89_write32_mask(rtwdev, reg, B_BE_PREBKF_TIME_NONAC_MASK,
SCH_PREBKF_24US);
}
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_EDCA_BCNQ_PARAM, mac_idx);
rtw89_write32_mask(rtwdev, reg, B_BE_BCNQ_CW_MASK, 0x32);
rtw89_write32_mask(rtwdev, reg, B_BE_BCNQ_AIFS_MASK, BCN_IFS_25US);
return 0;
}
static int addr_cam_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
{
u32 val32;
u16 val16;
u32 reg;
int ret;
ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
if (ret)
return ret;
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_ADDR_CAM_CTRL, mac_idx);
val32 = rtw89_read32(rtwdev, reg);
val32 = u32_replace_bits(val32, ADDR_CAM_SERCH_RANGE, B_BE_ADDR_CAM_RANGE_MASK);
val32 |= B_BE_ADDR_CAM_EN;
if (mac_idx == RTW89_MAC_0)
val32 |= B_BE_ADDR_CAM_CLR;
rtw89_write32(rtwdev, reg, val32);
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_ADDR_CAM_CTRL, mac_idx);
ret = read_poll_timeout_atomic(rtw89_read16, val16, !(val16 & B_BE_ADDR_CAM_CLR),
1, TRXCFG_WAIT_CNT, false, rtwdev, reg);
if (ret)
rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n");
return ret;
}
static int rtw89_mac_typ_fltr_opt_be(struct rtw89_dev *rtwdev,
enum rtw89_machdr_frame_type type,
enum rtw89_mac_fwd_target fwd_target,
u8 mac_idx)
{
u32 reg;
u32 val;
switch (fwd_target) {
case RTW89_FWD_DONT_CARE:
val = RX_FLTR_FRAME_DROP_BE;
break;
case RTW89_FWD_TO_HOST:
case RTW89_FWD_TO_WLAN_CPU:
val = RX_FLTR_FRAME_ACCEPT_BE;
break;
default:
rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n");
return -EINVAL;
}
switch (type) {
case RTW89_MGNT:
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_MGNT_FLTR, mac_idx);
break;
case RTW89_CTRL:
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CTRL_FLTR, mac_idx);
break;
case RTW89_DATA:
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_DATA_FLTR, mac_idx);
break;
default:
rtw89_err(rtwdev, "[ERR]set rx filter type err\n");
return -EINVAL;
}
rtw89_write32(rtwdev, reg, val);
return 0;
}
static int rx_fltr_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
{
u32 reg;
u32 val;
rtw89_mac_typ_fltr_opt_be(rtwdev, RTW89_MGNT, RTW89_FWD_TO_HOST, mac_idx);
rtw89_mac_typ_fltr_opt_be(rtwdev, RTW89_CTRL, RTW89_FWD_TO_HOST, mac_idx);
rtw89_mac_typ_fltr_opt_be(rtwdev, RTW89_DATA, RTW89_FWD_TO_HOST, mac_idx);
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RX_FLTR_OPT, mac_idx);
val = B_BE_A_BC_CAM_MATCH | B_BE_A_UC_CAM_MATCH | B_BE_A_MC |
B_BE_A_BC | B_BE_A_A1_MATCH | B_BE_SNIFFER_MODE |
u32_encode_bits(15, B_BE_UID_FILTER_MASK);
rtw89_write32(rtwdev, reg, val);
u32p_replace_bits(&rtwdev->hal.rx_fltr, 15, B_BE_UID_FILTER_MASK);
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PLCP_HDR_FLTR, mac_idx);
val = B_BE_HE_SIGB_CRC_CHK | B_BE_VHT_MU_SIGB_CRC_CHK |
B_BE_VHT_SU_SIGB_CRC_CHK | B_BE_SIGA_CRC_CHK |
B_BE_LSIG_PARITY_CHK_EN | B_BE_CCK_SIG_CHK | B_BE_CCK_CRC_CHK;
rtw89_write16(rtwdev, reg, val);
return 0;
}
static int cca_ctrl_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
{
return 0;
}
static int nav_ctrl_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
{
u32 val32;
u32 reg;
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_WMAC_NAV_CTL, mac_idx);
val32 = rtw89_read32(rtwdev, reg);
val32 &= ~B_BE_WMAC_PLCP_UP_NAV_EN;
val32 |= B_BE_WMAC_TF_UP_NAV_EN | B_BE_WMAC_NAV_UPPER_EN;
val32 = u32_replace_bits(val32, NAV_25MS, B_BE_WMAC_NAV_UPPER_MASK);
rtw89_write32(rtwdev, reg, val32);
return 0;
}
static int spatial_reuse_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)
{
u32 reg;
int ret;
ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
if (ret)
return ret;
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RX_SR_CTRL, mac_idx);
rtw89_write8_clr(rtwdev, reg, B_BE_SR_EN | B_BE_SR_CTRL_PLCP_EN);
reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_BSSID_SRC_CTRL, mac_idx);
rtw89_write8_set(rtwdev, reg, B_BE_PLCP_SRC_EN);
return 0;
}
static int tmac_init_be(struct rtw89_dev *rtwdev, u8 mac_idx)