{"payload":{"header_redesign_enabled":false,"results":[{"id":"24217298","archived":false,"color":"#b07219","followers":4440,"has_funding_file":false,"hl_name":"logisim-evolution/logisim-evolution","hl_trunc_description":"Digital logic design tool and simulator","language":"Java","mirror":false,"owned_by_organization":true,"public":true,"repo":{"repository":{"id":24217298,"name":"logisim-evolution","owner_id":84764158,"owner_login":"logisim-evolution","updated_at":"2024-05-28T03:45:09.662Z","has_issues":true}},"sponsorable":false,"topics":["education","simulator","fpga","vhdl","logic","circuits","verilog","circuit","digital-logic","logisim","digital-circuit","digital-circuits","timing-diagram","digital-logic-design","logisim-evolution"],"type":"Public","help_wanted_issues_count":70,"good_first_issue_issues_count":17,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":84,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Alogisim-evolution%252Flogisim-evolution%2B%2Blanguage%253AJava","metadata":null,"csrf_tokens":{"/logisim-evolution/logisim-evolution/star":{"post":"wIna4_ryYeP41E7I1bY7j-2dEaX1s7CUQBa4Fq0flqDmgXYJjQn2GZfEyyG_lZl05_7Y4SNOMKHVGuGxY6jKTg"},"/logisim-evolution/logisim-evolution/unstar":{"post":"XUBiy630-j6pyWgAKZ9HFMcF6S9hra5SO2s_PXKdhId6nym3oDu1FV24fy752RL4xlJhh7Abgw4V4cnQ55sK_Q"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"JDfXyEsC19g-ltfe4DJ_U3VhgHzsmjBf3BJWFHJc-ET0yS4rcFzRjpHWVR4AkAwfNgHsxjGHiDU45dzIkbwt2Q"}}},"title":"Repository search results"}