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I'd like to use the RAM component in my FPGA, but logisim doesn't support that component. My FPGA board itself has a 128kb RAM chip. And I want to connect some wires to a pulldown resistor connected to ground. What should I do in this case? Is there any way to use RAM? |
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The RAM component in Logisim-evolution can be synthesized only when using VHDL for netlisting. In Verilog it is not supported at the moment. PRs to add support for Verilog are welcome! Anyway, the RAM component will be mapped to the FPGA's block RAM. How much of that resource you have available depends on the exact type of your FPGA (check the datasheet). Interfacing with external RAM is not supported by Logisim-evolution, as this typically requires the usage of a RAM controller IP core, which depends on the type of RAM used on your FPGA development board. IMHO, this is out of scope for Logisim-evolution as a teaching tool. I am closing this issue as resolved. Feel free to reopen if you have further questions on this topic. |
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Thank you! |
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The RAM component in Logisim-evolution can be synthesized only when using VHDL for netlisting. In Verilog it is not supported at the moment. PRs to add support for Verilog are welcome! Anyway, the RAM component will be mapped to the FPGA's block RAM. How much of that resource you have available depends on the exact type of your FPGA (check the datasheet).
Interfacing with external RAM is not supported by Logisim-evolution, as this typically requires the usage of a RAM controller IP core, which depends on the type of RAM used on your FPGA development board. IMHO, this is out of scope for Logisim-evolution as a teaching tool.
I am closing this issue as resolved. Feel free to reopen if you h…