Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Add support for Acer Chromebook 515 Plus (CB515-2H) / Google Omnigul Platform #1663

Open
mdrobnak opened this issue May 5, 2024 · 1 comment

Comments

@mdrobnak
Copy link

mdrobnak commented May 5, 2024

Add support for the Acer Chromebook 515 Plus - CB515-2H, also known as the Google Omnigul / Brya.

lspci output:

00:00.0 Host bridge: Intel Corporation Device 4609 (rev 04)
00:02.0 VGA compatible controller: Intel Corporation Alder Lake-UP3 GT1 [UHD Graphics] (rev 0c)
00:04.0 Signal processing controller: Intel Corporation Alder Lake Innovation Platform Framework Processor Participant (rev 04)
00:08.0 System peripheral: Intel Corporation 12th Gen Core Processor Gaussian & Neural Accelerator (rev 04)
00:0a.0 Signal processing controller: Intel Corporation Platform Monitoring Technology (rev 01)
00:0d.0 USB controller: Intel Corporation Alder Lake-P Thunderbolt 4 USB Controller (rev 04)
00:12.0 Serial controller: Intel Corporation Alder Lake-P Integrated Sensor Hub (rev 01)
00:12.7 Universal Flash Storage controller: Intel Corporation Device 51ff (rev 01)
00:14.0 USB controller: Intel Corporation Alder Lake PCH USB 3.2 xHCI Host Controller (rev 01)
00:14.2 RAM memory: Intel Corporation Alder Lake PCH Shared SRAM (rev 01)
00:14.3 Network controller: Intel Corporation Alder Lake-P PCH CNVi WiFi (rev 01)
00:15.0 Serial bus controller: Intel Corporation Alder Lake PCH Serial IO I2C Controller #0 (rev 01)
00:15.1 Serial bus controller: Intel Corporation Alder Lake PCH Serial IO I2C Controller #1 (rev 01)
00:15.3 Serial bus controller: Intel Corporation Alder Lake PCH Serial IO I2C Controller #3 (rev 01)
00:16.0 Communication controller: Intel Corporation Alder Lake PCH HECI Controller (rev 01)
00:19.0 Serial bus controller: Intel Corporation Alder Lake-P Serial IO I2C Controller #0 (rev 01)
00:19.1 Serial bus controller: Intel Corporation Alder Lake-P Serial IO I2C Controller #1 (rev 01)
00:1e.0 Communication controller: Intel Corporation Alder Lake PCH UART #0 (rev 01)
00:1e.3 Serial bus controller: Intel Corporation Alder Lake SPI Controller (rev 01)
00:1f.0 ISA bridge: Intel Corporation Alder Lake PCH eSPI Controller (rev 01)
00:1f.3 Multimedia audio controller: Intel Corporation Alder Lake PCH-P High Definition Audio Controller (rev 01)
00:1f.5 Serial bus controller: Intel Corporation Alder Lake-P PCH SPI Controller (rev 01)
  • Already runs Coreboot
  • Intel iGPU "UHD Graphics"
  • 12th Gen Intel Core i3-1215U
  • Fixed 8 GB RAM
  • Fixed 128 GB UFS Storage [00:12.7 in lspci output]
  • Intel AX211 Wi-Fi 6E
  • 32MB Winbond chip - W25Q256JVEM

Work already being done in #1658.

@mdrobnak
Copy link
Author

Lifecycle Extension Guide from Acer - Shows how to disassemble parts of the laptop. [

Flash chip is on underside of board.

WSON8 6x8 mm probe necessary to unlock flash descriptor.

flashrom in Ubuntu 23.10 can reach chip using external programmer.

ifdtool used to unlock flash descriptor and enable HAP bit.

flashroom used to flash modified descriptor and machine boots fine.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

No branches or pull requests

1 participant