Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Investigate visibility to translate straight to LLVM IR metadata #1117

Closed
whitneywhtsang opened this issue May 13, 2024 · 2 comments · Fixed by #1087
Closed

Investigate visibility to translate straight to LLVM IR metadata #1117

whitneywhtsang opened this issue May 13, 2024 · 2 comments · Fixed by #1087
Assignees
@victor-eds
Labels
research
Milestone
0.3 [Triton] Lang...

Comments

@whitneywhtsang
Copy link
Contributor

No description provided.

@whitneywhtsang whitneywhtsang linked a pull request May 13, 2024 that will close this issue
[TritonGEN] Add triton_gen.cache_controls operation #1087
Merged
@etiotto
Copy link
Contributor

etiotto commented May 28, 2024

I think this is done now.

@etiotto etiotto closed this as completed May 28, 2024
@victor-eds
Copy link
Contributor

I think this is done now.

#1087 is still WIP

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees

@victor-eds victor-eds

Labels
research
Projects
None yet
Milestone
0.3 [Triton] Language and Runtime
Development

Successfully merging a pull request may close this issue.

[TritonGEN] Add triton_gen.cache_controls operation intel/intel-xpu-backend-for-triton
4 participants
@victor-eds @whitneywhtsang @etiotto @vlad-penkin