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VHDL "others" incompatibility #1194
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Hi It is not clear which line is causing Quartus to choke on the VHDL example so I am reposting the whole VDHL code with the offending line highlighted in bold (222). It doesn't help a lot but does give an idea where to find the issue in the original Slick-DMA.VHDL code Thanks, Andrew Lynch -- generated by Digital. Don't modify this file! LIBRARY ieee; -- 8-bit identity comparator architecture Behavioral of n74688 is LIBRARY ieee; entity DEMUX_GATE_2 is architecture Behavioral of DEMUX_GATE_2 is LIBRARY ieee; -- dual 2-line to 4-line decoder/demultiplexer architecture Behavioral of n74139 is LIBRARY ieee; entity MUX_GATE_BUS_1 is
end MUX_GATE_BUS_1; architecture Behavioral of MUX_GATE_BUS_1 is LIBRARY ieee; -- quad 2-line to 1-line data selectors/multiplexers architecture Behavioral of n74157 is LIBRARY ieee; entity DIG_D_FF_AS_BUS is architecture Behavioral of DIG_D_FF_AS_BUS is
end Behavioral; LIBRARY ieee; -- quad D-flip-flop architecture Behavioral of n74175 is LIBRARY ieee; entity main is architecture Behavioral of main is |
Hi
I've been experimenting some more with Digital exports to Quartus for compilation/synthesis into a CPLD. This time I am exporting my design to VHDL and importing into Quartus. My project has two MAX7128S-10 CPLDs; the one for CPU glue logic and another for DMA glue logic. The CPU glue logic CPLD seems to import and compile/synthesize fine using VHDL. However, when I try the same with the DMA glue logic VHDL I get an error message in Quartus. Maybe this is a Quartus problem not Digital but I thought I'd bring it to your attention regardless in case there is something that can be done about it in Digital.
The module in VHDL code is this one (line 222):
Here are the specific error messages. Relates to "others" in line 222:
I hope this helps, Thanks, Andrew Lynch
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