Too Many Variables

[jessaskey]

Hi there... I have a circuit which has 28 TTL IC's in the design and when I hit the 'Analyze' button I get the error of "Too many variables (inputs + flip-flops), 24 are allowed but 103 were found. I do have a large number of IO pins (Targeting an ATF1504-84pin) with 45.

Is there a way I can increase the limit just to get a JEDEC file generated? (I understand how some of the other things like the Truth tables etc would be excessive).

Wonderful software, I am learning a lot and this is my first foray into CPLDs! Thank you!

[jessaskey]

and... Im following up on my own post in hopes that it may help someone else.... I found by looking at the source that the MAX_INPUTS_ALLOWED is set to 24. I following the next instructions here that got me set up with a compilation environment. I updated the MAX_INPUTS_ALLOWED to 250 and am compiling now... I have a few test errors that Im tracking down... will report back.

[jessaskey]

.. got it compiled... I was getting errors with maven-surefire-plugin so I ignored and used the build command below and the JAR compiled up great! Now the 'Analyze' command is running... the truth table is quite large and it has been sitting on the "Equations are being Calculated" message for about 30 minutes so far.... will wait patiently and see if it finishes overnight, my CPU isn't doing much tho so Im thinking I may need to run digital.jar with an increased memory space to give it a little more 'oomph!'

mvn install -DskipTests

[hneemann]

So far, the simulator only supports exact solution methods to determine a logic function from a truth table. This means that the determined logic function is guaranteed to be minimal, i.e. that there is no simpler normal form.
The problem is that the complexity of this method (Quine-McCluskey algorithm) grows exponentially with the number of inputs. Both in terms of computing time and memory consumption.
There are other methods (Espresso heuristic logic minimizer) whose runtime does not grow exponentially, but which do not guarantee a minimal solution. These are more suitable for functions with many inputs. Unfortunately, I have not yet got around to implementing this.

[jessaskey]

Should I be careful to minimize the value of MAX_INPUTS_ALLOWED to my exact count or is the code/minimizer written in such a way that having a higher MAX_INPUTS_ALLOWED has absolutely no bearing on the Quine-McClusky algorithm? I think I just set it at 250 for mine which only has 103.

[hneemann]

It doesn't matter. As soon as the number of inputs reaches 20 or so, it will no longer be possible to calculate a solution in a reasonable time. This hard limit is only there to prevent the user from having the feeling that the simulator has crashed. It is better to display an error message than to calculate indefinitely. Especially as the JVM is only busy with garbage collection after a very short time, as the memory consumption also increases significantly. This can only be solved by a different, non-exponential algorithm, not by adjusting a few constants.

I would also doubt that the result would fit into an ATF1504, as it is not "fully connected". I would try to decouple the circuit by introducing some additional flip-flops. This has a better chance of success. This is also the reason why I could not motivate myself to implement the espresso algorithm: In most cases, the result wouldn't help anyway.

[jessaskey]

Okay, thank you for your responses. Understood on what you are saying. I think there is potential for me to pull apart my ~30 TTL IC's into sub-circuits too.... I will read up on your docs on the sub-circuit approach... I do have a nice section of the circuit which is 7 TTL ICs (4 - 74374, 2 - 74283 and 1 74244) that is duplicated... so I think I may be able to break this down a bit instead of trying to do this all in one .dig file. Im really trying to determine if this will fit into either the 1504 or 1508 because if not, probably have to go a completely different direction. thank you again for your software, it is very well written.

[hneemann]

It does not matter how many subcircuits a circuit is divided into. It only depends on how many different inputs/flip-flop outputs an output or a flip-flop input depends on. This number is not only limited by the analysis algorithm but also by the target hardware. And since the ATF1504 is not "fully connected", I don't think that an output or flip-flop can depend on 103 other flip-flops or inputs. But I can't say for sure. The ATF1504 has some cascading options.