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The\nconfigured value from the macro needs to be stored in a const to avoid\n-Werror=type-limits errors when configured to be zero.\n\nChange-Id: Ida96e0816ac914ed69d6fd82ad90ebe89cdef1cc\nSigned-off-by: Peter Marheine \nReviewed-on: https://review.coreboot.org/c/flashrom/+/81606\nTested-by: build bot (Jenkins) \nReviewed-by: Anastasia Klimchuk ","shortMessageHtmlLink":"Make sleep threshold for delays configurable"}},{"before":"e558ef1fb9c261c7a39ec50bef4f71505958dab0","after":"5737ff972e8361b6ebf673b8954e86cb6a28da46","ref":"refs/heads/main","pushedAt":"2024-05-06T10:17:48.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"coreboot-org-bot","name":"coreboot.org bot","path":"/coreboot-org-bot","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/46246920?s=80&v=4"},"commit":{"message":"flashrom_tester: Correct \"WP screw\" message\n\nflashrom_tester prints hints on how to modify hardware write protect\nstate as follows:\n\n...\n > connect the battery (and/or open the WP screw)\n...\n > disconnect the battery (and/or open the WP screw)\n...\n\nThe first advice should be \"[...] close the WP screw\".\n\nTEST=`flashrom_tester --flashrom_binary=$(which flashrom) \\\n internal Erase_and_Write Fail_to_verify`\n\nChange-Id: I45f06db51e92e68bf724b13bdf5b31bba511d270\nSigned-off-by: Brian Norris \nReviewed-on: https://review.coreboot.org/c/flashrom/+/82083\nReviewed-by: Hsuan-ting Chen \nReviewed-by: Evan Benn \nReviewed-by: Anastasia Klimchuk \nReviewed-by: Angel Pons \nTested-by: build bot (Jenkins) ","shortMessageHtmlLink":"flashrom_tester: Correct \"WP screw\" message"}},{"before":"c2bb2eff4c93f22266a72b0dcbfdedcc5d8a456f","after":"e558ef1fb9c261c7a39ec50bef4f71505958dab0","ref":"refs/heads/main","pushedAt":"2024-05-03T04:17:52.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"coreboot-org-bot","name":"coreboot.org bot","path":"/coreboot-org-bot","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/46246920?s=80&v=4"},"commit":{"message":"flashchips: Add support for MXIC MX25L1633E\n\nThe MX25L1633E has been tested by ch341a programmer : read, write,\nerase and wp.\n\nWe have tested --wp-enable, --wp-disable, --wp-list and --wp-range\ncommands for write-protect feature.\n\nMX25L1633E datasheet is available at the following URL:\nhttps://www.macronix.com/Lists/Datasheet/Attachments/8617/MX25L1633E,%203V,%2016Mb,%20v1.8.pdf\n\nChange-Id: I63ee0182ad6e62b7408136285aa0e927d53f7bc8\nSigned-off-by: DanielZhang \nReviewed-on: https://review.coreboot.org/c/flashrom/+/81836\nTested-by: build bot (Jenkins) \nReviewed-by: Anastasia Klimchuk ","shortMessageHtmlLink":"flashchips: Add support for MXIC MX25L1633E"}},{"before":"183208b5cb397c9b58762900502e6b1b0a358ae6","after":"c2bb2eff4c93f22266a72b0dcbfdedcc5d8a456f","ref":"refs/heads/main","pushedAt":"2024-04-29T10:16:15.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"coreboot-org-bot","name":"coreboot.org bot","path":"/coreboot-org-bot","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/46246920?s=80&v=4"},"commit":{"message":"flashchips: Add support for MXIC MX25L3239E\n\nThe MX25L3239E has been tested by ch341a programmer : read, write,\nerase and wp.\n\nWe have tested --wp-enable, --wp-disable, --wp-list and --wp-range\ncommands for write-protect feature.\n\nMX25L3239E datasheet is available at the following URL:\nhttps://www.mxic.com.tw/Lists/Datasheet/Attachments/8613/MX25L3239E,%203V,%2032Mb,%20v1.3.pdf\n\nChange-Id: Ic7a848028fe937deb1bf83ef2a9dddf1330334b6\nSigned-off-by: DanielZhang \nReviewed-on: https://review.coreboot.org/c/flashrom/+/81563\nTested-by: build bot (Jenkins) \nReviewed-by: Anastasia Klimchuk ","shortMessageHtmlLink":"flashchips: Add support for MXIC MX25L3239E"}},{"before":"a79ec2425e31899293b1b50d3f7ef790a207f06f","after":"183208b5cb397c9b58762900502e6b1b0a358ae6","ref":"refs/heads/main","pushedAt":"2024-04-26T00:16:09.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"coreboot-org-bot","name":"coreboot.org bot","path":"/coreboot-org-bot","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/46246920?s=80&v=4"},"commit":{"message":"udelay: only use OS time for delays, except on DOS\n\nAs proposed on the mailing list (\"RFC: remove the calibrated delay\nloop\" [1]), this removes the calibrated delay loop and uses OS-based\ntiming functions for all delays because the calibrated delay loop can\ndelay for shorter times than intended.\n\nWhen sleeping this now uses nanosleep() unconditionally, since usleep\nwas only used on DOS (where DJGPP lacks nanosleep). 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The old implementation is reused\nwith some branches removed based on the knowledge that timer resolution\nwill not be better than about 50 milliseconds.\n\nTested by reading and writing flash on several Intel and AMD systems:\n\n * Lenovo P920 (Intel C620, read/verify only)\n * \"nissa\" chromebook (Intel Alder Lake-N)\n * \"zork\" chromebook (AMD Zen+)\n\n[1]: https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/thread/HFH6UHPAKA4JDL4YKPSQPO72KXSSRGME/\n\nSigned-off-by: Peter Marheine \nChange-Id: I7ac5450d194a475143698d65d64d8bcd2fd25e3f\nReviewed-on: https://review.coreboot.org/c/flashrom/+/81545\nReviewed-by: Anastasia Klimchuk \nTested-by: build bot (Jenkins) \nReviewed-by: Brian Norris ","shortMessageHtmlLink":"udelay: only use OS time for delays, except on DOS"}},{"before":"be95e0be1f106f717a0aadfc5bf63f310ded8435","after":"a79ec2425e31899293b1b50d3f7ef790a207f06f","ref":"refs/heads/main","pushedAt":"2024-04-22T08:16:24.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"coreboot-org-bot","name":"coreboot.org bot","path":"/coreboot-org-bot","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/46246920?s=80&v=4"},"commit":{"message":"flashchips: Split and add write-protect support for MX25L12833F\n\nMX25L12833F datasheet: https://www.macronix.com/Lists/Datasheet/Attachments/8934/MX25L12833F,%203V,%20128Mb,%20v1.0.pdf\nStatus register: page 30 table 7 (BP0~BP3, SRWD)\nConfiguration register: page 31 table 8 (TB)\nSecurity register: page 57 table 12 (WPSEL)\n\nMX25L12835F datasheet:\nhttps://www.macronix.com/Lists/Datasheet/Attachments/8653/MX25L12835F,%203V,%20128Mb,%20v1.6.pdf\nStatus register: page 31(BP0~BP3, SRWD)\nConfiguration register: page 32 table 7 (TB)\nSecurity register: page 61 table 9 (WPSEL)\n\nMX25L12845E datasheet: (no CONFIG)\nhttps://www.mxic.com.tw/Lists/Datasheet/Attachments/8693/MX25L12845E,%203V,%20128Mb,%20v1.9.pdf\nStatus register: page 17 (BP0~BP3, SRWD)\nSecurity register: page 29 (WPSEL)\n\nMX25L12865E datasheet: (no CONFIG)\nhttps://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L6465E,_MX25L12865E.pdf\nStatus register: page 19 (BP0~BP3, SRWD)\nSecurity register: page 31 (WPSEL)\n\nMX25L12873F datasheet: (no hardware WP)\nhttps://www.mxic.com.tw/Lists/Datasheet/Attachments/8652/MX25L12873F,%203V,%20128Mb,%20v1.2.pdf\nStatus register: page 31(BP0~BP3, SRWD)\nConfiguration register: page 32 table 7 (TB)\nSecurity register: page 60 table 9 (WPSEL)\n\nSplits the MX25L12833F/MX25L12835F/MX25L12845E/MX25L12865E/MX25L12873F\ngroup into three subgroups:\n* MX25L12833F: This chip have the configuration register and WP tested\n* MX25L12835F/MX25L12873F: These chips have the configuration register.\n* MX25L12845E/MX25L12865E: These chips don't have the configuration\n register.\n\nTests the write protect functionality on the MX25L12833F chip only.\n\nBUG=b:332486637\nTEST=Test flashrom --wp-disable with MX25L12833FZNI-10 on ChromeOS\n\nChange-Id: I379c833eea3ed3487504126f45c6df672a772ddc\nSigned-off-by: Hsuan Ting Chen \nReviewed-on: https://review.coreboot.org/c/flashrom/+/81792\nTested-by: build bot (Jenkins) \nReviewed-by: Anastasia Klimchuk ","shortMessageHtmlLink":"flashchips: Split and add write-protect support for MX25L12833F"}},{"before":"85f14efe065504a81dc803ad34bdaa669176d3eb","after":"be95e0be1f106f717a0aadfc5bf63f310ded8435","ref":"refs/heads/main","pushedAt":"2024-04-22T06:15:48.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"coreboot-org-bot","name":"coreboot.org bot","path":"/coreboot-org-bot","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/46246920?s=80&v=4"},"commit":{"message":"flashchips: Add write protect function support for MX25R1635F\n\nThe MX25R1635F has been tested by ch341a programmer : read, write,\nerase and wp.\n\nWe have tested --wp-enable, --wp-disable, --wp-list and --wp-range\ncommands for write-protect feature.\n\nMX25R1635F datasheet is available at the following URL:\nhttps://www.macronix.com/Lists/Datasheet/Attachments/8702/MX25R1635F,%20Wide%20Range,%2016Mb,%20v1.6.pdf\n\nChange-Id: I6e2b417ab177039618069d8e35132ddbfb814f03\nSigned-off-by: DanielZhang \nReviewed-on: https://review.coreboot.org/c/flashrom/+/81840\nTested-by: build bot (Jenkins) \nReviewed-by: Anastasia Klimchuk ","shortMessageHtmlLink":"flashchips: Add write protect function support for MX25R1635F"}},{"before":"e5ed0c6340961594dcf1a22f9907d91d576b4885","after":"85f14efe065504a81dc803ad34bdaa669176d3eb","ref":"refs/heads/main","pushedAt":"2024-04-21T10:16:47.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"coreboot-org-bot","name":"coreboot.org bot","path":"/coreboot-org-bot","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/46246920?s=80&v=4"},"commit":{"message":"ich: Add names for region 5, 9, 10, 11, 12, 15\n\nAdd Region 9 for Intel Meteor Lake; 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It is useful to have OS specific instructions as a link\nto share with people.\n\nChange-Id: I78645131b1f0acbedcf11964a204a24c45b62cff\nSigned-off-by: Anastasia Klimchuk \nReviewed-on: https://review.coreboot.org/c/flashrom/+/81780\nTested-by: build bot (Jenkins) \nReviewed-by: Patrick Georgi","shortMessageHtmlLink":"doc: Make OS specific instructions as headers so they are linkable"}},{"before":"124b6eaf6babb292d871594f61fc2b15fda28f31","after":"7bc347e16d9845d078631a95f7a0fab57b9c47c9","ref":"refs/heads/main","pushedAt":"2024-04-12T06:15:34.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"coreboot-org-bot","name":"coreboot.org bot","path":"/coreboot-org-bot","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/46246920?s=80&v=4"},"commit":{"message":"Makefile: Fix cleanup for Sphinx versions prior to 4.x\n\nFixup for change I9cd280551a1ba4d17edb2e857d56f80431b61e1b.\n\nChange-Id: I123aec7cf2f016ba905c220cfc84a217523f9932\nSigned-off-by: Anton Samsonov \nReviewed-on: https://review.coreboot.org/c/flashrom/+/81802\nTested-by: build bot (Jenkins) \nReviewed-by: Anastasia Klimchuk ","shortMessageHtmlLink":"Makefile: Fix cleanup for Sphinx versions prior to 4.x"}},{"before":"2a5d2920d8817f1bc7e479a2ed868a6e2a46dcbe","after":"124b6eaf6babb292d871594f61fc2b15fda28f31","ref":"refs/heads/main","pushedAt":"2024-04-10T04:16:29.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"coreboot-org-bot","name":"coreboot.org bot","path":"/coreboot-org-bot","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/46246920?s=80&v=4"},"commit":{"message":"meson: Update CI script to enforce building man pages and docs\n\n`test_build.sh` is used by Jenkins, therefore it should build\neverything. Docker container for Jenkins is expected to have all\nthe dependencies installed, and if some of them are missing, script\nshould fail.\n\nRecently we had a situation when docker image was missing sphinx\nand flashrom Jenkins was silently skipping building man-pages and\ndocumentation. This patch prevents this happening again, because\nbuilding man pages and docs will be enforced.\n\nChange-Id: Ib89abddad27d1168cf0a621cf4bdb9f541266165\nSigned-off-by: Anastasia Klimchuk \nReviewed-on: https://review.coreboot.org/c/flashrom/+/81665\nReviewed-by: Martin L Roth \nTested-by: build bot (Jenkins) \nReviewed-by: Anton Samsonov ","shortMessageHtmlLink":"meson: Update CI script to enforce building man pages and docs"}},{"before":"041644a6afb12232495c45d3450ae0b3e2eb2a2d","after":"2a5d2920d8817f1bc7e479a2ed868a6e2a46dcbe","ref":"refs/heads/main","pushedAt":"2024-04-02T04:15:55.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"coreboot-org-bot","name":"coreboot.org bot","path":"/coreboot-org-bot","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/46246920?s=80&v=4"},"commit":{"message":"serprog: Add SPI Mode and CS Mode commands\n\nThis commit adds two new commands to the serprog protocol which allow\nmore fine grained control over the SPI bus. This enables more\napplications over serprog like e.g. flashing AVR microcontrollers.\nThis can be tried with my forks of pico-serprog:\n\nhttps://github.com/funkeleinhorn/pico-serprog/tree/spimode\n\nand avrdude:\n\nhttps://github.com/funkeleinhorn/avrgirl/tree/serprog-programmer\n\nI announced this change in flashrom and flashprog IRC channels and got\noverall positive feedback in the flashprog channel. The same changes\nwill be sent to flashprog to prevent diverging specs.\n\nChange-Id: Idb5a9a3710fede322def5191d68b7fba0e135292\nSigned-off-by: Funkeleinhorn \nReviewed-on: https://review.coreboot.org/c/flashrom/+/81428\nReviewed-by: Anastasia Klimchuk \nTested-by: build bot (Jenkins) ","shortMessageHtmlLink":"serprog: Add SPI Mode and CS Mode commands"}},{"before":"1bcedfa598a3a266d4eee3c836921dec5f6a9f0c","after":"041644a6afb12232495c45d3450ae0b3e2eb2a2d","ref":"refs/heads/main","pushedAt":"2024-03-30T13:13:37.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"coreboot-org-bot","name":"coreboot.org bot","path":"/coreboot-org-bot","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/46246920?s=80&v=4"},"commit":{"message":"classic_cli_manpage.rst: Update doc for custom_rst of raiden_debug_spi\n\nUpdate technical details for custom_rst of raiden_debug_spi to help\nusers better understand their configuration options.\n\nBUG=b:161745002\nBRANCH=none\nTEST=`meson compile -C testdir` and\n view ./testdir/doc/html/classic_cli_manpage.html\n\nChange-Id: Ie2b084a3ed9bf40f91bfa81dbc95ec69d99d5ad0\nSigned-off-by: Hsuan Ting Chen \nReviewed-on: https://review.coreboot.org/c/flashrom/+/81114\nReviewed-by: Anastasia Klimchuk \nTested-by: build bot (Jenkins) ","shortMessageHtmlLink":"classic_cli_manpage.rst: Update doc for custom_rst of raiden_debug_spi"}},{"before":"435309ea28200a1e103e64d5a63e394f70adaf40","after":"1bcedfa598a3a266d4eee3c836921dec5f6a9f0c","ref":"refs/heads/main","pushedAt":"2024-03-30T09:15:25.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"coreboot-org-bot","name":"coreboot.org bot","path":"/coreboot-org-bot","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/46246920?s=80&v=4"},"commit":{"message":"flashchips: Add support for MXIC MX25L12850F\n\nThe MX25L12850F has been tested by ch341a programmer : read, write,\nerase and wp.\n\nWe have tested --wp-enable, --wp-disable, --wp-list and --wp-range\ncommands for write-protect feature.\n\nMX25L12850F datasheet is available at the following URL:\nhttps://www.macronix.com/Lists/Datasheet/Attachments/8632/MX25L12850F,%203V,%20128Mb,%20v1.0.pdf\n\nChange-Id: I71ac70d273904f94d015401f9d8df587084efad0\nSigned-off-by: DanielZhang \nReviewed-on: https://review.coreboot.org/c/flashrom/+/81350\nReviewed-by: Alexander Goncharov \nTested-by: build bot (Jenkins) \nReviewed-by: Anastasia Klimchuk ","shortMessageHtmlLink":"flashchips: Add support for MXIC MX25L12850F"}},{"before":"b65f347377b2f6166bd6af09f73d67f41af3a92b","after":"435309ea28200a1e103e64d5a63e394f70adaf40","ref":"refs/heads/main","pushedAt":"2024-03-27T23:14:44.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"coreboot-org-bot","name":"coreboot.org bot","path":"/coreboot-org-bot","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/46246920?s=80&v=4"},"commit":{"message":"doc/dev_guide: Add section about Jenkins build, and scan-build\n\nChange-Id: I416b632c55d1ceb925456ac8c8947dfbcef2e888\nSigned-off-by: Anastasia Klimchuk \nReviewed-on: https://review.coreboot.org/c/flashrom/+/81261\nReviewed-by: Stefan Reinauer \nTested-by: build bot (Jenkins) \nReviewed-by: Peter Marheine ","shortMessageHtmlLink":"doc/dev_guide: Add section about Jenkins build, and scan-build"}},{"before":"70e1a41eaddea9f81dd674e333a985ecac2c12f8","after":"b65f347377b2f6166bd6af09f73d67f41af3a92b","ref":"refs/heads/main","pushedAt":"2024-03-26T07:15:48.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"coreboot-org-bot","name":"coreboot.org bot","path":"/coreboot-org-bot","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/46246920?s=80&v=4"},"commit":{"message":"flashchips: Add Zetta Device ZD25LQ128\n\nDatasheet: http://www.zettadevice.com/uploads/files/163410630201e3483211247ac1.pdf\n\nTested probe, read, erase, write, verify on ZD25LQ128AWIG chips\nusing Linux SPI and DediProg SF100 programmers.\n\nRenamed ZETTADEVICE_ macros to ZETTA_ to accomodate longer suffixes.\n\nChange-Id: I5cb20158e81ab109f16958285b8787858efb4831\nSigned-off-by: Anton Samsonov \nReviewed-on: https://review.coreboot.org/c/flashrom/+/81392\nTested-by: build bot (Jenkins) \nReviewed-by: Anastasia Klimchuk ","shortMessageHtmlLink":"flashchips: Add Zetta Device ZD25LQ128"}},{"before":"9cc6be205dce4cb67de3c1202bdd0769547ede22","after":"70e1a41eaddea9f81dd674e333a985ecac2c12f8","ref":"refs/heads/main","pushedAt":"2024-03-21T13:15:27.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"coreboot-org-bot","name":"coreboot.org bot","path":"/coreboot-org-bot","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/46246920?s=80&v=4"},"commit":{"message":"cli_common: Add link to the documentation how to mark chip tested\n\nPerhaps some of the users will be able to follow the instructions\nand send a patch to mark chip as tested. The option to send report\nto the mailing list remains available as before.\n\nChange-Id: I36105725058f2fecb82408c369b70b3324502ece\nSigned-off-by: Anastasia Klimchuk \nReviewed-on: https://review.coreboot.org/c/flashrom/+/81266\nReviewed-by: Sergii Dmytruk \nTested-by: build bot (Jenkins) \nReviewed-by: Peter Marheine ","shortMessageHtmlLink":"cli_common: Add link to the documentation how to mark chip tested"}},{"before":"54b053e6b23715fbefa59b71d2cc5211508f2d79","after":"9cc6be205dce4cb67de3c1202bdd0769547ede22","ref":"refs/heads/main","pushedAt":"2024-03-21T11:14:30.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"coreboot-org-bot","name":"coreboot.org bot","path":"/coreboot-org-bot","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/46246920?s=80&v=4"},"commit":{"message":"serprog: Fix scan-build warning of resource leak\n\nWarning found by the latest scan-build run:\n\n*** CID 1534883: (RESOURCE_LEAK)\n/serprog.c: 853 in serprog_init()\n847 \"by programmer!\\n\", cs_num8);\n848\t\t\t\tgoto init_err_cleanup_exit;\n849 }\n850 }\n851 bt = serprog_buses_supported;\n852 if (sp_docommand(S_CMD_S_BUSTYPE, 1, &bt, 0, NULL))\n>>>CID 1534883: (RESOURCE_LEAK)\n>>>Variable \"cs\" going out of scope leaks the storage it points to.\n853 goto init_err_cleanup_exit;\n854 }\n\nFollow up on\ncommit e8c350f55e596aae3ab2bbc210b68389e2301a6c\n\nChange-Id: Id9cf211de3c482f702adebfcfa274a183c83a33f\nSigned-off-by: Anastasia Klimchuk \nReviewed-on: https://review.coreboot.org/c/flashrom/+/81032\nTested-by: build bot (Jenkins) \nReviewed-by: Alexander Goncharov \nReviewed-by: Stefan Reinauer ","shortMessageHtmlLink":"serprog: Fix scan-build warning of resource leak"}},{"before":"537050351a2c1819c06cdd2019ce18014986fa75","after":"54b053e6b23715fbefa59b71d2cc5211508f2d79","ref":"refs/heads/main","pushedAt":"2024-03-14T11:14:32.000Z","pushType":"push","commitsCount":3,"pusher":{"login":"coreboot-org-bot","name":"coreboot.org bot","path":"/coreboot-org-bot","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/46246920?s=80&v=4"},"commit":{"message":"udelay: Lower the sleep vs delay threshold\n\nBy default, we busy-loop (a.k.a., \"delay\") for most delay values, and\nonly allow sleeping for large delays. But busy-looping is expensive, as\nit wastes CPU cycles.\n\nIn a simple program that runs a bunch of samples of [1] over 1000\nsamples, I find that for 0.1 s (100000 us):\n\n 64x2 AMD CPU (CONFIG_HZ=250 / CONFIG_NO_HZ_FULL=y):\n min diff: 60 us\n max diff: 831 us\n mean diff: 135 us\n\n 4+2 Mediatek MT8183 CPU (CONFIG_HZ=1000 / CONFIG_NO_HZ_IDLE=y /\n sysctl kernel.timer_highres=1):\n min diff: 70 us\n max diff: 1556 us\n mean diff: 146 us\n\n 4+2 Mediatek MT8183 CPU (CONFIG_HZ=1000 / CONFIG_NO_HZ_IDLE=y /\n sysctl kernel.timer_highres=0):\n min diff: 94 us\n max diff: 7222 us\n mean diff: 1201 us\n\ni.e., maximum 1.5% error, typically ~0.1% error with high resolution\ntimers. Max 7% error, typical 1% error with low resolution timers. The\nerror is always in the positive direction (i.e., sleep longer than the\nrequested delay, not shorter than the request).\n\nThis seems reasonable.\n\n[1] Stripped / pseudocode:\n\n clock_gettime(CLOCK_MONOTONIC, before);\n nanosleep({ .tv_nsec = usecs * 1000 }, NULL);\n clock_gettime(CLOCK_MONOTONIC, after);\n diff = abs((after - before) / 1000 - usecs));\n\nChange-Id: Ifd4821c66c5564f7c975c08769a6742f645e9be0\nSigned-off-by: Brian Norris \nReviewed-on: https://review.coreboot.org/c/flashrom/+/80808\nReviewed-by: Anastasia Klimchuk \nTested-by: build bot (Jenkins) ","shortMessageHtmlLink":"udelay: Lower the sleep vs delay threshold"}},{"before":"7be490758efc8a72be5b1b0095b871d25c53cdf4","after":"537050351a2c1819c06cdd2019ce18014986fa75","ref":"refs/heads/main","pushedAt":"2024-03-10T21:13:48.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"coreboot-org-bot","name":"coreboot.org bot","path":"/coreboot-org-bot","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/46246920?s=80&v=4"},"commit":{"message":"doc: Update arbitration team to be flashrom specific\n\nSame approach as it was before: founder and current project lead.\n\nChange-Id: I1043b9499ab22da5ec981592d7b4311f027c4b5f\nSigned-off-by: Anastasia Klimchuk \nReviewed-on: https://review.coreboot.org/c/flashrom/+/81106\nReviewed-by: Stefan Reinauer \nTested-by: build bot (Jenkins) ","shortMessageHtmlLink":"doc: Update arbitration team to be flashrom specific"}},{"before":"f2a750475a0a3ed375ad08738b3c9e163b4c2433","after":"7be490758efc8a72be5b1b0095b871d25c53cdf4","ref":"refs/heads/main","pushedAt":"2024-03-08T13:12:53.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"coreboot-org-bot","name":"coreboot.org bot","path":"/coreboot-org-bot","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/46246920?s=80&v=4"},"commit":{"message":"fmap: Update major/minor version check\n\nIt's not valid to separately check the major and minor versions. The\nproper minor check would be something like:\n\n if (fmap->ver_major == FMAP_VER_MAJOR &&\n fmap->ver_minor > FMAP_VER_MINOR)\n ERROR();\n\nBut this code was alleged (at introduction in [1]) to have come from\ncbfstool, and cbfstool doesn't bother with a minor version check. This\ncheck is only for finding the FMAP while searching the flash; it isn't\nactually here for integrity and compatibility purpose.\n\nDrop the MINOR version check; align with cbfstool on the MAJOR version\ncheck; and match the cbfstool comments for is_valid_fmap(), to emphasize\nthe lack of precision.\n\n[1] Commit c82900b66142 (\"Add support to get layout from fmap (e.g.\n coreboot rom)\")\n\nBRANCH=none\nBUG=b:288327526\nTEST=libflashrom + ChromiumOS flashmap\n\nChange-Id: I984835579d3b257a2462906f1f5091b179891bd0\nSigned-off-by: Brian Norris \nReviewed-on: https://review.coreboot.org/c/flashrom/+/79060\nTested-by: build bot (Jenkins) \nReviewed-by: Anastasia Klimchuk ","shortMessageHtmlLink":"fmap: Update major/minor version check"}}],"hasNextPage":true,"hasPreviousPage":false,"activityType":"all","actor":null,"timePeriod":"all","sort":"DESC","perPage":30,"cursor":"djE6ks8AAAAETKzV-wA","startCursor":null,"endCursor":null}},"title":"Activity ยท flashrom/flashrom"}