{"payload":{"feedbackUrl":"https://github.com/orgs/community/discussions/53140","repo":{"id":70746484,"defaultBranch":"main","name":"tvm","ownerLogin":"apache","currentUserCanPush":false,"isFork":false,"isEmpty":false,"createdAt":"2016-10-12T22:20:28.000Z","ownerAvatar":"https://avatars.githubusercontent.com/u/47359?v=4","public":true,"private":false,"isOrgOwned":true},"refInfo":{"name":"","listCacheKey":"v0:1717239870.0","currentOid":""},"activityList":{"items":[{"before":"4ab91d4c4fb20aee02717b08f0597e06fb2675bd","after":"b87d1f9b0124877769d537d4748c63546d2b2d8b","ref":"refs/heads/main","pushedAt":"2024-06-02T11:43:09.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"tqchen","name":"Tianqi Chen","path":"/tqchen","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/2577440?s=80&v=4"},"commit":{"message":"[Runtime] Stateless interface of PagedKVCache leaf node commit (#17057)\n\nThis PR changes the interface of the function\n`CommitAcceptedTokenTreeNodeToKVCache` introduced recently for\nPagedKVCache to a stateless interface. Previously the interace\nis a stateful one, which makes strong assumption on the caller\nside. This commit removes the assumption so that the interface\nbecomes less confusing.","shortMessageHtmlLink":"[Runtime] Stateless interface of PagedKVCache leaf node commit (#17057)"}},{"before":"515c07937bbf9c0bd7575928217c258caaa5867c","after":"4ab91d4c4fb20aee02717b08f0597e06fb2675bd","ref":"refs/heads/nightly","pushedAt":"2024-06-02T05:02:37.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"github-actions[bot]","name":null,"path":"/apps/github-actions","primaryAvatarUrl":"https://avatars.githubusercontent.com/in/15368?s=80&v=4"},"commit":{"message":"Use adapter.info when available instead of requestAdapterInfo (#17051)\n\n* Use adapter.info when available instead of requestAdapterInfo\r\n\r\n* Update package.json","shortMessageHtmlLink":"Use adapter.info when available instead of requestAdapterInfo (#17051)"}},{"before":"7c2d52810b4061ab794f4e029c653e264fb3dc21","after":null,"ref":"refs/heads/dependabot/pip/docker/python/requests-2.32.0","pushedAt":"2024-06-01T11:04:30.000Z","pushType":"branch_deletion","commitsCount":0,"pusher":{"login":"dependabot[bot]","name":null,"path":"/apps/dependabot","primaryAvatarUrl":"https://avatars.githubusercontent.com/in/29110?s=80&v=4"}},{"before":null,"after":"743c428d37ef7bb3e122262f35eadc840804a9f8","ref":"refs/heads/dependabot/pip/apps/microtvm/requests-2.32.2","pushedAt":"2024-06-01T11:04:25.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"dependabot[bot]","name":null,"path":"/apps/dependabot","primaryAvatarUrl":"https://avatars.githubusercontent.com/in/29110?s=80&v=4"},"commit":{"message":"Bump requests from 2.28.2 to 2.32.2 in /apps/microtvm\n\nBumps [requests](https://github.com/psf/requests) from 2.28.2 to 2.32.2.\n- [Release notes](https://github.com/psf/requests/releases)\n- [Changelog](https://github.com/psf/requests/blob/main/HISTORY.md)\n- [Commits](https://github.com/psf/requests/compare/v2.28.2...v2.32.2)\n\n---\nupdated-dependencies:\n- dependency-name: requests\n dependency-type: indirect\n...\n\nSigned-off-by: dependabot[bot] ","shortMessageHtmlLink":"Bump requests from 2.28.2 to 2.32.2 in /apps/microtvm"}},{"before":"31f47215965b3a4d58a0ee1f450965a43ce2fcd0","after":"4ab91d4c4fb20aee02717b08f0597e06fb2675bd","ref":"refs/heads/main","pushedAt":"2024-06-01T11:02:10.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"tqchen","name":"Tianqi Chen","path":"/tqchen","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/2577440?s=80&v=4"},"commit":{"message":"Use adapter.info when available instead of requestAdapterInfo (#17051)\n\n* Use adapter.info when available instead of requestAdapterInfo\r\n\r\n* Update package.json","shortMessageHtmlLink":"Use adapter.info when available instead of requestAdapterInfo (#17051)"}},{"before":"515c07937bbf9c0bd7575928217c258caaa5867c","after":"31f47215965b3a4d58a0ee1f450965a43ce2fcd0","ref":"refs/heads/main","pushedAt":"2024-06-01T11:01:56.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"tqchen","name":"Tianqi Chen","path":"/tqchen","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/2577440?s=80&v=4"},"commit":{"message":"[Runtime] Support PagedKVCache with tree attention (#17049)\n\n* [Runtime] Support PagedKVCache with tree attention\r\n\r\nThis PR introduces the tree attention to PagedKVCache. With this\r\nfeature, now the KV cache is ready for tree attention cases such as\r\nspeculative decoding trees.\r\n\r\nThis PR adds tree attention tests to test the correctness.\r\n\r\nThe changes in this PR to KVState interface are backward compatible.\r\n\r\n* Update kv_state.cc\r\n\r\n* Update kv_state.cc\r\n\r\n---------\r\n\r\nCo-authored-by: Tianqi Chen ","shortMessageHtmlLink":"[Runtime] Support PagedKVCache with tree attention (#17049)"}},{"before":"1eac17857fc95a28e1cbaf90a9c34575807622e1","after":"515c07937bbf9c0bd7575928217c258caaa5867c","ref":"refs/heads/nightly","pushedAt":"2024-06-01T05:03:37.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"github-actions[bot]","name":null,"path":"/apps/github-actions","primaryAvatarUrl":"https://avatars.githubusercontent.com/in/15368?s=80&v=4"},"commit":{"message":"[DLight] Skip GEMV rules when more than one vector (#17052)\n\nThe current dlight GEMV rule require only one vector buffer, otherwise\r\nraise an error. This PR change this behavior to skip the rule.","shortMessageHtmlLink":"[DLight] Skip GEMV rules when more than one vector (#17052)"}},{"before":"1eac17857fc95a28e1cbaf90a9c34575807622e1","after":"515c07937bbf9c0bd7575928217c258caaa5867c","ref":"refs/heads/main","pushedAt":"2024-05-31T14:26:50.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"tqchen","name":"Tianqi Chen","path":"/tqchen","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/2577440?s=80&v=4"},"commit":{"message":"[DLight] Skip GEMV rules when more than one vector (#17052)\n\nThe current dlight GEMV rule require only one vector buffer, otherwise\r\nraise an error. This PR change this behavior to skip the rule.","shortMessageHtmlLink":"[DLight] Skip GEMV rules when more than one vector (#17052)"}},{"before":"71f7af7985e2c883494a9aa80e0f5d12c154a990","after":"1eac17857fc95a28e1cbaf90a9c34575807622e1","ref":"refs/heads/nightly","pushedAt":"2024-05-31T05:02:42.000Z","pushType":"push","commitsCount":6,"pusher":{"login":"github-actions[bot]","name":null,"path":"/apps/github-actions","primaryAvatarUrl":"https://avatars.githubusercontent.com/in/15368?s=80&v=4"},"commit":{"message":"[Runtime] Fix PagedKVCache for PopN and enhance tests (#17045)\n\nThis PR fixes a bug in the PagedKVCache which may happen when the\r\nsequence removal order is not consistent with the reverse order\r\nof sequence add/fork order. With this fix, the PagedKVCache now\r\nsupports removing sequences in any order without breaking.\r\n\r\nThis PR also adds an `empty` function to PagedKVCache to check if\r\nthe KV cache is empty. Right now this function is only used for test\r\npurpose, where we check if everything in the KV cache is freed after\r\nremoving all sequences.","shortMessageHtmlLink":"[Runtime] Fix PagedKVCache for PopN and enhance tests (#17045)"}},{"before":"820f1b617a4f8ccf196803c5e48a4f155c929c4a","after":"1eac17857fc95a28e1cbaf90a9c34575807622e1","ref":"refs/heads/main","pushedAt":"2024-05-30T19:13:12.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"tqchen","name":"Tianqi Chen","path":"/tqchen","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/2577440?s=80&v=4"},"commit":{"message":"[Runtime] Fix PagedKVCache for PopN and enhance tests (#17045)\n\nThis PR fixes a bug in the PagedKVCache which may happen when the\r\nsequence removal order is not consistent with the reverse order\r\nof sequence add/fork order. With this fix, the PagedKVCache now\r\nsupports removing sequences in any order without breaking.\r\n\r\nThis PR also adds an `empty` function to PagedKVCache to check if\r\nthe KV cache is empty. Right now this function is only used for test\r\npurpose, where we check if everything in the KV cache is freed after\r\nremoving all sequences.","shortMessageHtmlLink":"[Runtime] Fix PagedKVCache for PopN and enhance tests (#17045)"}},{"before":"7c2c0d9337f3b353576bccc30f61c16abcc633a7","after":"820f1b617a4f8ccf196803c5e48a4f155c929c4a","ref":"refs/heads/main","pushedAt":"2024-05-30T16:41:03.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"tqchen","name":"Tianqi Chen","path":"/tqchen","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/2577440?s=80&v=4"},"commit":{"message":"[Runtime] Compatibility with dmlc::Stream API changes (#16998)\n\n* [Runtime] Compatibility with dmlc::Stream API changes\r\n\r\nThis commit updates TVM implementations of `dmlc::Stream`. With\r\nhttps://github.com/dmlc/dmlc-core/pull/686, this API now requires\r\nthe `Write` method to return the number of bytes written. This change\r\nallows partial writes to be correctly handled.\r\n\r\n* Update dmlc-core version\r\n\r\n* lint fix","shortMessageHtmlLink":"[Runtime] Compatibility with dmlc::Stream API changes (#16998)"}},{"before":"f6aab98ace3c7c15df309b5a89f39ac3e92e5a6c","after":"7c2c0d9337f3b353576bccc30f61c16abcc633a7","ref":"refs/heads/main","pushedAt":"2024-05-30T11:28:50.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"tqchen","name":"Tianqi Chen","path":"/tqchen","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/2577440?s=80&v=4"},"commit":{"message":"[Disco][QoL] Implement broadcast/scatter methods for Session (#17035)\n\n* [Disco][QoL] Implement broadcast/scatter methods for Session\r\n\r\nPrior to this commit, use of the `disco.Session` API to broadcast or\r\nscatter an array required several steps from the caller.\r\n\r\n1. Allocate memory on worker0\r\n2. Transfer data from the controller to worker0\r\n3. Allocate memory on each worker\r\n4. Broadcast/scatter data from worker0 to all workers\r\n\r\nWhile exposing these steps is necessary for performance, especially\r\nwhen used repeatedly, it can be tedious/error-prone to use for\r\ninitialization that is only performed once.\r\n\r\nThis commit adds utility methods `Session.broadcast` and\r\n`Session.scatter`, which are implemented in terms of the existing\r\nlower-level methods `Session.broadcast_from_worker0` and\r\n`Session.scatter_from_worker0`. These methods perform the transfer\r\nfrom the controller to worker0, and from worker0 to all other\r\nworkers.\r\n\r\n* lint fix","shortMessageHtmlLink":"[Disco][QoL] Implement broadcast/scatter methods for Session (#17035)"}},{"before":"08b32a797642515b0b263ead292af6962fea0cf4","after":"f6aab98ace3c7c15df309b5a89f39ac3e92e5a6c","ref":"refs/heads/main","pushedAt":"2024-05-30T11:28:35.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"tqchen","name":"Tianqi Chen","path":"/tqchen","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/2577440?s=80&v=4"},"commit":{"message":"[Bugfix][Support] Fix copy constructor for support::OrderedSet (#17044)\n\nPrior to this commit, the `support::OrderedSet` utility used the\r\ndefault copy constructor and copy assignment, which would copy both\r\nthe `OrderedSet::elements_` and `OrderedSet::elem_to_iter_` members.\r\nWhile this is the correct behavior for `elements_`, the copy of\r\n`elem_to_iter_` would contain references to the original's `element_`,\r\nrather than to its own.\r\n\r\nWhile `elem_to_iter_` is used in both `OrderedSet::push_back` and\r\n`OrderedSet::erase`, the implementation of `OrderedSet::push_back`\r\nonly depends on the keys used in `elem_to_iter_`, and does not depend\r\non the values stored. As a result, this bug could go undetected for\r\nappend-only usage, which is the most frequent use of `OrderedSet`.\r\n\r\nThis commit updates `support::OrderedSet` to have an explicit copy\r\nconstructor and copy assignment. Only the `std::list elements_`\r\nmember may be copied, while the `elem_to_iter_` must instead be\r\nrebuilt.","shortMessageHtmlLink":"[Bugfix][Support] Fix copy constructor for support::OrderedSet (#17044)"}},{"before":"291c04770a079254d812007c191ae6923857312c","after":"08b32a797642515b0b263ead292af6962fea0cf4","ref":"refs/heads/main","pushedAt":"2024-05-30T11:28:26.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"tqchen","name":"Tianqi Chen","path":"/tqchen","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/2577440?s=80&v=4"},"commit":{"message":"[Runtime][ROCm] Enable ROCm host memory support (#17037)\n\nThis PR enables the ROCMHost memory support in ROCm device API.","shortMessageHtmlLink":"[Runtime][ROCm] Enable ROCm host memory support (#17037)"}},{"before":"71f7af7985e2c883494a9aa80e0f5d12c154a990","after":"291c04770a079254d812007c191ae6923857312c","ref":"refs/heads/main","pushedAt":"2024-05-30T08:02:52.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"ekalda","name":"Elen Kalda","path":"/ekalda","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/15799086?s=80&v=4"},"commit":{"message":"[TIR] Fix Bug in VectorizeLoop (#17039)\n\n* [TIR] Fix Bug in VectorizeLoop\r\n\r\nThis PR fixes a bug in vectorize loop introduced\r\nrelated to recent change.\r\n\r\nThe visit to condition can write need scalarize to true\r\nthen the followup visit to then case can trigger an ICHECK.\r\n\r\nThe visit to let value can also write need scalarize flag\r\nin which case we need to immediately scalarize.\r\n\r\n* Add unit test\r\n\r\n---------\r\n\r\nCo-authored-by: tqchen ","shortMessageHtmlLink":"[TIR] Fix Bug in VectorizeLoop (#17039)"}},{"before":"c9d87ef54fbba29b16a0a8420fb61c669808a256","after":"71f7af7985e2c883494a9aa80e0f5d12c154a990","ref":"refs/heads/nightly","pushedAt":"2024-05-30T05:02:43.000Z","pushType":"push","commitsCount":4,"pusher":{"login":"github-actions[bot]","name":null,"path":"/apps/github-actions","primaryAvatarUrl":"https://avatars.githubusercontent.com/in/15368?s=80&v=4"},"commit":{"message":"[Runtime] Use preferred host memory (pinned memory) in KV cache (#17036)\n\nThis PR updates the PagedKVCache with the pinned memory support,\r\nwhich can reduce the copy overhead between CPU and GPU.\r\n\r\nThis PR also bumps FlashInfer version, which now supports\r\n* specifying kernels to build via cmake,\r\n* pinned memory as host memory.\r\n\r\nWe also update CMakeLists.txt and config.cmake to include the\r\nFlashInfer compile options. Prior to this PR, the kernels being\r\nbuilt is hardcoded in FlashInfer header files.","shortMessageHtmlLink":"[Runtime] Use preferred host memory (pinned memory) in KV cache (#17036)"}},{"before":"8bdd54b2fd652f064dc7b0f56a89688fb555bf1e","after":"71f7af7985e2c883494a9aa80e0f5d12c154a990","ref":"refs/heads/main","pushedAt":"2024-05-29T21:14:17.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"tqchen","name":"Tianqi Chen","path":"/tqchen","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/2577440?s=80&v=4"},"commit":{"message":"[Runtime] Use preferred host memory (pinned memory) in KV cache (#17036)\n\nThis PR updates the PagedKVCache with the pinned memory support,\r\nwhich can reduce the copy overhead between CPU and GPU.\r\n\r\nThis PR also bumps FlashInfer version, which now supports\r\n* specifying kernels to build via cmake,\r\n* pinned memory as host memory.\r\n\r\nWe also update CMakeLists.txt and config.cmake to include the\r\nFlashInfer compile options. Prior to this PR, the kernels being\r\nbuilt is hardcoded in FlashInfer header files.","shortMessageHtmlLink":"[Runtime] Use preferred host memory (pinned memory) in KV cache (#17036)"}},{"before":"d9240e4814b33993d8720a488abfd2571131908f","after":"8bdd54b2fd652f064dc7b0f56a89688fb555bf1e","ref":"refs/heads/main","pushedAt":"2024-05-29T15:44:46.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"tqchen","name":"Tianqi Chen","path":"/tqchen","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/2577440?s=80&v=4"},"commit":{"message":"[TOPI] Fix SME conv2d schedule import and intrin argument (#17040)\n\nFixes a merge conflict between #16981 and #17003.\r\n\r\nChange-Id: Ifcc983ef0b8c00250568a048fd682933adfdcde4","shortMessageHtmlLink":"[TOPI] Fix SME conv2d schedule import and intrin argument (#17040)"}},{"before":"7afac14ebd0f22a5a53c51d362a5bc853fb1c868","after":"d9240e4814b33993d8720a488abfd2571131908f","ref":"refs/heads/main","pushedAt":"2024-05-29T11:43:42.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"tqchen","name":"Tianqi Chen","path":"/tqchen","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/2577440?s=80&v=4"},"commit":{"message":"[Relax][Bugfix] Apply FuseOps to nested DataflowBlock (#17033)\n\nWhile it is ill-formed for control-flow to occur within a\r\n`DataflowBlock`, it is legal for a `DataflowBlock` to be contained\r\nwithin a control-flow. Prior to this commit, the `FuseOps` and\r\n`FuseOpsByPattern` transforms erroneously skipped `DataflowBlock`\r\ninstances that were contained within a `relax::If` node.\r\n\r\nThis commit updates `FuseOps` to apply operator fusion to any dataflow\r\nblock, regardless of whether it is found at the top level of a a Relax\r\nfunction.\r\n\r\nCo-authored-by: Chris Sullivan ","shortMessageHtmlLink":"[Relax][Bugfix] Apply FuseOps to nested DataflowBlock (#17033)"}},{"before":"c9d87ef54fbba29b16a0a8420fb61c669808a256","after":"7afac14ebd0f22a5a53c51d362a5bc853fb1c868","ref":"refs/heads/main","pushedAt":"2024-05-29T08:41:33.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"lhutton1","name":"Luke Hutton","path":"/lhutton1","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/35535092?s=80&v=4"},"commit":{"message":"[BugFix][MSC] split name_string with index by colon from the right (#17000)\n\nFixes a naming mismatch in MSCGraph where tensor_name could formatted as\r\n'string:index:index',and the corresponding node.name is 'string:index'.\r\nSplitting tensor_name from the right aligns it correctly.\r\n\r\nFor example, the TFLite default input name 'serving_default_input:0'\r\nbecomes 'serving_default_input:0:0' in MSCGraph, while node.name remains\r\n'serving_default_input:0'.","shortMessageHtmlLink":"[BugFix][MSC] split name_string with index by colon from the right (#…"}},{"before":"b598f28a1cecabf95a1986dcc55a864c8c9ab743","after":"c9d87ef54fbba29b16a0a8420fb61c669808a256","ref":"refs/heads/nightly","pushedAt":"2024-05-29T05:04:43.000Z","pushType":"push","commitsCount":6,"pusher":{"login":"github-actions[bot]","name":null,"path":"/apps/github-actions","primaryAvatarUrl":"https://avatars.githubusercontent.com/in/15368?s=80&v=4"},"commit":{"message":"[Relax][Bugfix] Annotate ComputePrimValue output as host function (#17032)\n\nThe `ComputePrimValue` transform is used to compute the value of\r\nsymbolic expressions that may appear within a Relax function. For\r\nexample, to compute a boolean condition used for a `relax::If` node.\r\nThese functions are used for small host-side computations, prior to\r\nlaunching a device kernel.\r\n\r\nThis commit updates `ComputePrimValue` to annotate the generated\r\n`PrimFunc` with `tir::attr::kIsHostFunc`. This annotation is required\r\nfor correct behavior in `tvm.dlight.ApplyDefaultSchedule`, to avoid\r\nerroneous scheduling of this function for the GPU, and for\r\n`tir::transform::BindTarget`, to ensure that the function is compiled\r\nfor execution on the host.\r\n\r\nCo-authored-by: Chris Sullivan ","shortMessageHtmlLink":"[Relax][Bugfix] Annotate ComputePrimValue output as host function (#1…"}},{"before":"b2c61162f006504b192493e9ceeac9b89a87da65","after":"c9d87ef54fbba29b16a0a8420fb61c669808a256","ref":"refs/heads/main","pushedAt":"2024-05-29T00:49:20.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"tqchen","name":"Tianqi Chen","path":"/tqchen","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/2577440?s=80&v=4"},"commit":{"message":"[Relax][Bugfix] Annotate ComputePrimValue output as host function (#17032)\n\nThe `ComputePrimValue` transform is used to compute the value of\r\nsymbolic expressions that may appear within a Relax function. For\r\nexample, to compute a boolean condition used for a `relax::If` node.\r\nThese functions are used for small host-side computations, prior to\r\nlaunching a device kernel.\r\n\r\nThis commit updates `ComputePrimValue` to annotate the generated\r\n`PrimFunc` with `tir::attr::kIsHostFunc`. This annotation is required\r\nfor correct behavior in `tvm.dlight.ApplyDefaultSchedule`, to avoid\r\nerroneous scheduling of this function for the GPU, and for\r\n`tir::transform::BindTarget`, to ensure that the function is compiled\r\nfor execution on the host.\r\n\r\nCo-authored-by: Chris Sullivan ","shortMessageHtmlLink":"[Relax][Bugfix] Annotate ComputePrimValue output as host function (#1…"}},{"before":null,"after":"b71a9a3827d81ac17da5f5bc608583f1a02bd0d8","ref":"refs/heads/revert-17003-sme-conv2d-fp32","pushedAt":"2024-05-28T23:56:33.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"tqchen","name":"Tianqi Chen","path":"/tqchen","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/2577440?s=80&v=4"},"commit":{"message":"Revert \"[SME][TOPI] Add conv2d NHWC SME fp32 schedule (#17003)\"\n\nThis reverts commit cab54e0dee82f84d94cd65f8fe0432ee1c2f2e22.","shortMessageHtmlLink":"Revert \"[SME][TOPI] Add conv2d NHWC SME fp32 schedule (#17003)\""}},{"before":"d4b096f905ad32be448c3a188ecf93a14c5734d5","after":"b2c61162f006504b192493e9ceeac9b89a87da65","ref":"refs/heads/main","pushedAt":"2024-05-28T23:52:01.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"tqchen","name":"Tianqi Chen","path":"/tqchen","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/2577440?s=80&v=4"},"commit":{"message":"[Relax][Bugfix] Bind symbolic variables in R.match_cast (#17034)\n\nPrior to this commit, variable replacement by `BindSymbolicVars` would\r\nfail to replace variables that occur within a `relax::MatchCast` node.\r\nThis pattern is rare, because the `bind_symbolic_vars` method can only\r\nreplace variables that are exposed as part of the function signature,\r\nand most uses of `relax::MatchCast` act as a definition for symbolic\r\nvariables that are not exposed through the function signature. This\r\npattern is well-formed, though, since the `relax::MatchCast` node can\r\nalso act as a user of previously-defined symbolic variables.\r\n\r\nThe root cause for this bug was in the `ExprMutator` visitor for\r\n`relax::MatchCast`, which did not visit the struct info field. As a\r\nresult, the virtual `ExprMutator::VisitPrimExpr` function was not\r\ncalled for expressions that occur within the `StructInfo` of a\r\n`relax::MatchCast`. This commit updates `ExprMutator` to resolve this\r\nbug, and applies an analogous fix for `ExprVisitor`.\r\n\r\nCo-authored-by: Chris Sullivan ","shortMessageHtmlLink":"[Relax][Bugfix] Bind symbolic variables in R.match_cast (#17034)"}},{"before":"cab54e0dee82f84d94cd65f8fe0432ee1c2f2e22","after":"d4b096f905ad32be448c3a188ecf93a14c5734d5","ref":"refs/heads/main","pushedAt":"2024-05-28T17:35:06.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"tqchen","name":"Tianqi Chen","path":"/tqchen","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/2577440?s=80&v=4"},"commit":{"message":"[Web] Fix string to uint8 array for special characters (#17031)","shortMessageHtmlLink":"[Web] Fix string to uint8 array for special characters (#17031)"}},{"before":"430e02fdcd2516ff4084e4d3c545fc7faa38893a","after":"cab54e0dee82f84d94cd65f8fe0432ee1c2f2e22","ref":"refs/heads/main","pushedAt":"2024-05-28T16:30:22.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"ekalda","name":"Elen Kalda","path":"/ekalda","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/15799086?s=80&v=4"},"commit":{"message":"[SME][TOPI] Add conv2d NHWC SME fp32 schedule (#17003)\n\nThis commit adds a scalable `arm_cpu` conv2d NHWC schedule for fp32 which generates SME instructions by using the tensor intrinsics introduced in #16921.\r\n\r\nAlongside the SME schedule, the logic of the TE schedule `schedule_conv2d_gemm_native()` for both non-scalable and scalable vector implementations has also been translated into the new TIR schedule. This means that the TE compute definition `compute_conv2d_NHWC_hybrid()` is now compatible with both the original TE schedules (e.g. `schedule_conv2d_NHWC_hybrid()`) and the newly introduced TIR schedule `schedule_conv2d_NHWC_hybrid_TIR()`. The corresponding TOPI test has been extended to reflect that.","shortMessageHtmlLink":"[SME][TOPI] Add conv2d NHWC SME fp32 schedule (#17003)"}},{"before":"20d8c537316758ba13017f2c7dc9e5de77ecf069","after":"430e02fdcd2516ff4084e4d3c545fc7faa38893a","ref":"refs/heads/main","pushedAt":"2024-05-28T14:54:50.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"ekalda","name":"Elen Kalda","path":"/ekalda","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/15799086?s=80&v=4"},"commit":{"message":"[SME] Add scalable fp16->fp32 dense schedule (#16981)\n\nThis commit extends the functionality of the SME dense and matmul\r\nschedules to support operations with fp16 inputs and an fp32 output,\r\nwhere `transpose_a=False` and `transpose_b=True`.\r\n\r\nFor convenience, it also adds a utility called `get_vscale_factor`\r\nwhich created the correct multiplier for `vscale` given a data type,\r\nreflecting ideas from an early design of the\r\n[SVE](https://github.com/apache/tvm-rfcs/pull/104) RFC.","shortMessageHtmlLink":"[SME] Add scalable fp16->fp32 dense schedule (#16981)"}},{"before":"b598f28a1cecabf95a1986dcc55a864c8c9ab743","after":"20d8c537316758ba13017f2c7dc9e5de77ecf069","ref":"refs/heads/main","pushedAt":"2024-05-28T10:15:30.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"leandron","name":"Leandro Nunes","path":"/leandron","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/437416?s=80&v=4"},"commit":{"message":"[SVE] Add support for representing and creating buffer-level predicates (#16966)\n\n* [SVE] Add support for representing and creating buffer-level predicates\r\n\r\nRepresentation\r\n--------------\r\nThis commit extends `BufferLoad` and `BufferStore` to accept a predicate\r\nmask argument indicating which lanes in a vectorized buffer load/store\r\nshould be read/written.\r\n\r\nAs a simple example, we can load all lanes:\r\n```\r\ntir.BufferLoad(buf, [tir.Ramp(0, 1, 8)], predicate=tir.Broadcast(1, 8))\r\n```\r\n\r\nOr disable loading all lanes:\r\n```\r\ntir.BufferLoad(buf, [tir.Ramp(0, 1, 8)], predicate=tir.Broadcast(0, 8))\r\n```\r\n\r\nIn TVMScript, buffer loads and stores are currently displayed using a\r\n\"short-hand\" notation e.g. `A[0:4]`, but there was no clear path for\r\nextending this notation to support predicates. Therefore, a \"long-hand\"\r\nnotation is introduced e.g. `A.load([T.Ramp(0, 1, 4)], predicate=...)`.\r\nThe TVMScript printer falls back to the long-hand notation whenever\r\npredicates are specified.\r\n\r\nCreation\r\n--------\r\nBuffer-level predication becomes more motivating when combined with the\r\n`tir.get_active_lane_mask` intrinsic. It can be used to mask off lanes\r\nwhen the vectorized axis is not divisible by the vector length. A\r\ndetailed example and rationale can be found in the\r\n[RFC](https://github.com/apache/tvm-rfcs/blob/main/rfcs/0104-scalable-vectors-in-tir.md#predication).\r\n\r\nPredicated buffer load/stores are created in the `VectorizeLoop` pass\r\nvia `TryPredicateBufferAccesses`. This pass aims to convert block-level\r\npredicates e.g.\r\n```\r\nfor i_0 in T.serial(4):\r\n for i_1 in T.vectorized(4):\r\n if i_0 * 4 + i_1 < 14:\r\n B[i_0 * 4 + i_1] = A[i_0 * 4 + i_1] + 1.0\r\n```\r\nto buffer-level predicates, e.g.\r\n```\r\nfor i_0 in T.serial(4):\r\n predicate = T.get_active_lane_mask(\"int1x4\", i_0 * 4, 14)\r\n A_load = T.meta_var(A.load([T.Ramp(i_0 * 4, 1, 4)], predicate=predicate))\r\n B.store(A_load, [T.Ramp(i_0 * 4, 1, 4)], predicate=predicate)\r\n```\r\nIt takes a conservative approach for now, focussing only on expressions\r\nproduced by the split scheduling primitive, but more complex expressions\r\ncould be supported in the future.\r\n\r\n`TryPredicateBufferAccesses` can be explicitly enabled/disabled with the\r\n`tir.enable_buffer_level_predication` pass context option. By default it\r\nwill be disabled, unless the target supports SVE, in which case it will\r\nbe enabled by default.\r\n\r\nCo-authored-by: Elen Kalda \r\nCo-authored-by: Neil Hickey \r\n\r\nChange-Id: Idde259a7d7e4536f00ed3a1dafedd0a5d24a1593\r\n\r\n* Fix lint and correct test config option name\r\n\r\nChange-Id: I864475c3d03e9b426ce5ef987989216d57f3e019\r\n\r\n* Address review comments\r\n\r\nThis includes:\r\n* Taking into account possibility of target being overridden in\r\n the vectorize pass.\r\n* Predicate PrimExpr -> Optional\r\n* Checking that predicate is not used for any target that doesn't\r\n support it.\r\n* Use vload/vstore API as opposed to load/store\r\n* int1 mask -> uint1 mask for boolean representation. This is converted\r\n to int1 in the LLVM backend.\r\n\r\nChange-Id: I4da0705352e321f6be6333a5bb777caa6a6ca9ef\r\n\r\n* Fix lint\r\n\r\nChange-Id: Idd3f3593fe524f3444487c520d947dfd53386db0\r\n\r\n* Fix some failing tests\r\n\r\n* vload/vstore updates that were missed previously\r\n* int1 -> bool updates\r\n* fix gpu target tests\r\n\r\nFixes a test and updates comments referencing old load/store api\r\n\r\nChange-Id: I26a0c480d2dedee442ca0116909a7751d1dfa9ac\r\n\r\n* Address comments\r\n\r\n- Correct doc strings\r\n- Correct typo in error message\r\n- Add some additional checks for BufferLoad\r\n\r\nChange-Id: Ie25563d569c0ed729ac915a6ba3a724a9e191014\r\n\r\n* Account for buffer lanes in predicate lane check\r\n\r\nChange-Id: I821210665e36c26bfa37fc9ed380b5d03c9e816e","shortMessageHtmlLink":"[SVE] Add support for representing and creating buffer-level predicat…"}},{"before":"27a3b90105c27135924a357fb72c4d6bfa5e33d7","after":"b598f28a1cecabf95a1986dcc55a864c8c9ab743","ref":"refs/heads/nightly","pushedAt":"2024-05-28T05:02:41.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"github-actions[bot]","name":null,"path":"/apps/github-actions","primaryAvatarUrl":"https://avatars.githubusercontent.com/in/15368?s=80&v=4"},"commit":{"message":"[Contrib] Implement NDArray cache update (#17029)","shortMessageHtmlLink":"[Contrib] Implement NDArray cache update (#17029)"}},{"before":"7359313b40dd1927cd27e2c60539575ae08a4dc5","after":"b598f28a1cecabf95a1986dcc55a864c8c9ab743","ref":"refs/heads/main","pushedAt":"2024-05-27T13:25:15.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"tqchen","name":"Tianqi Chen","path":"/tqchen","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/2577440?s=80&v=4"},"commit":{"message":"[Contrib] Implement NDArray cache update (#17029)","shortMessageHtmlLink":"[Contrib] Implement NDArray cache update (#17029)"}}],"hasNextPage":true,"hasPreviousPage":false,"activityType":"all","actor":null,"timePeriod":"all","sort":"DESC","perPage":30,"cursor":"djE6ks8AAAAEWiUt7gA","startCursor":null,"endCursor":null}},"title":"Activity · apache/tvm"}