Unexpected alignment error

[euro-phd]

Hi, I'm studying MIPS64 at uni as part of the Computer Architecture course. One of the labs requires us to execute the following code:

.text
div.d f7,f9,f10
mul.d f2,f4,f3
sub.d f7,f7,f4
ld r1,78(r0)
add.d f4,f5,f6
halt

During the execution, using EduMIPS64, the error occurs.

However, on WinMIPS64, used by a lecturer, everything runs smoothly.

Is there a way to patch/reconfigure EduMIPS64 to receive the same results as WinMIPS64? It seems like WinMIPS64 fixed alignment on its own. However, I'm unsure how to code the same behavior in EduMIPS64.

Thanks

[lupino3]

Hi @euro-phd, thanks a lot for raising this issue!

I think that in this case EduMIPS64 deals with misaligned load instructions correctly.
If you look at the the MIPS64 ISA documentation (https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MIPS_Architecture_MIPS64_InstructionSet_%20AFP_P_MD00087_06.05.pdf), you'll see that LD requires the operand to be aligned to 8 bytes. (we implemented this before release 6)

When we implemented load/store, we also saw that there were patents for handling non-aligned memory accesses, so we decided to only support aligned memory accesses. See #2.

In your example, given that the memory is empty, is there a chance you can run

ld r1, 72(r0)

or

ld r1, 80(r0)

instead of the instruction that causes a problem?

Hope this helps, thanks!

[lupino3]

This is also documented in the manual: https://edumips64.readthedocs.io/en/latest/instructions.html#load-store-instructions

[lupino3]

HI, I'm not sure exactly how much work would be required. Every load/store instruction needs to be modified. The semantics are in Appendix B of the most recent MIPS64 ISA spec, I have created an issue to track your request and I'll try to investigate the implementation it as time permits: #703 Thanks, Andrea Il giorno dom 28 ago 2022 alle ore 16:20 wa1tf0r.me < ***@***.***> ha scritto:

…

Thank you for answering my question. Now I understand more about MIPS64 and how to work with it. Nevertheless, I wonder how many changes are needed to handle non-aligned memory accesses, just as an option that can be turned on in settings. — Reply to this email directly, view it on GitHub <#701 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AABQ3S2BTN3M7GFBGSGZAGLV3NYSVANCNFSM573BQ2EA> . You are receiving this because you commented.Message ID: ***@***.***>

-- Andrea Spadaccini, Ph.D. About me: https://about.me/andreaspadaccini a.k.a. lupino3 / spadaccio